Apple Xserve G5 manual Gigahertz Frontside Bus, Point-to-Point System Controller

Technology Overview 14

Xserve G5

Xeon Xeon PowerPC G5 PowerPC G5

Industry’s fastest frontside bus

The dual-channel frontside bus allows data to travel to and from the PowerPC G5 processor at the same time. On dual processor systems, each PowerPC G5 has its own dedicated interface to maximize throughput—com- pared with dual Xeon-based systems, in which the processors must share a single bus.

Gigahertz Frontside Bus

To harness the power of the G5 processor, a 64-bit Double Data Rate (DDR) frontside bus speeds up communication between the PowerPC G5 and the memory controller. Unlike conventional processor interfaces, which carry data in only one direction at

a time, this dual-channel frontside bus has two 32-bit point-to-point links: One link travels into the processor and another travels from the processor, which means no wait time while the processor and the system controller negotiate which will use the bus or while the bus switches direction. This elastic interface self-tunes during startup for optimal signal quality.

On the 2GHz PowerPC G5, the frontside bus operates at 1GHz for a total theoretical bandwidth of up to 8GB/s. Dual processor systems get an even greater performance boost, because each PowerPC G5 has a dedicated frontside bus. This unique feature results in a maximum aggregate raw bandwidth of 16GB/s on dual 2GHz Xserve G5 systems. This is well over twice the 6.4GB/s maximum throughput of Itanium 2–based systems and almost four times the 4.3GB/s throughput of Xeon-based systems. Because there’s a dedicated data path in each direction, transaction-intensive server operations execute fast and without contention for data—so the processor doesn’t sit idle, waiting for data to arrive.

On dual processor systems, the two independent frontside buses allow each PowerPC G5 to handle its own tasks at maximum speed with minimal interruption. They also enable each processor to discover and access data in the other processor’s caches,

a technique called intervention, or snooping. Cache intervention guarantees cache coherency, which ensures that the processor always fetches the correct data, even if the data has been modified and is stored in the cache of the other processor.

Point-to-Point System Controller

A new system controller is central to the overall performance of Xserve G5. This revolutionary application-specific integrated circuit (ASIC)—built using advanced IBM technology—is one of the industry’s fastest. A superefficient point-to-point architec- ture provides each primary subsystem with dedicated throughput to main memory, so massive amounts of data can traverse the system without contention for band- width. In contrast, subsystems on Xeon-based servers must share bandwidth, which can result in time-consuming arbitration while they negotiate for access across a common data path.

Advanced ECC Memory Technology

Xserve G5 maximizes the efficiency of its computing power with an advanced 128-bit DDR memory architecture and support for up to 8GB of RAM. This high-speed, high- capacity memory architecture enables video encoding, transaction-intensive network- ing, and scientific applications to perform radically faster. What’s more, it works with ECC logic in the system controller to protect data from corruption or errors.

Double Data Rate (DDR) memory

Xserve G5 features a memory controller that supports 400MHz, 128-bit DDR SDRAM. With fast DDR memory and a wider 128-bit interface that addresses two banks of SDRAM at a time, Xserve G5 can reach a memory throughput of up to 6.4GB/s—more than double the throughput of the G4-based Xserve. For even greater performance, direct memory access (DMA) works with the point-to-point system controller, so subsystems can access main memory without needing to interact with the processor.