Apple Xserve G5 manual Technical Specifications, Hardware, Processor, Memory, Connections

Technology Overview 28

Xserve G5

Technical Specifications

Hardware

Processor

•Single or dual 2GHz PowerPC G5 processors

•PowerPC processor architecture with 64-bit data paths and registers

•Native support for 32-bit application code

•512K on-chip L2 cache running at processor speed

•Parallel execution architecture supporting up to 215 simultaneous in-flight instructions

•Simultaneous issue of up to 10 out-of-order operations

•Dual-pipeline Velocity Engine for 128-bit single-instruction, multiple-data (SIMD) processing

•Two independent double-precision floating-point units

•Two integer units

•Advanced three-component branch prediction logic

•64-bit, 1GHz DDR frontside bus per processor, each supporting up to 8GB/s data throughput

•Point-to-point system controller with support for ECC memory

Memory

•128-bit data paths for up to 6.4GB/s memory throughput

•512MB or1GB of PC3200 (400MHz) DDR SDRAM

•Data protection using Error Correction Code (ECC) logic

•Eight slots supporting up to 8GB of DDR SDRAM using the following DIMMs (in pairs):

–256MB DIMMs (128-bit-wide, 128- or 256-Mbit technology)

–512MB DIMMs (64-bit-wide, 256-Mbit technology)

–1GB DIMMs (64-bit-wide, 256-Mbit technology)

I/O connections

•Two open11-inch, 64-bit PCI-X slots, running at up to133MHz with one card installed or up to 100MHz with two cards installed; support for 32-bit or 64-bit 3.3V Universal PCI cards running at 33MHz or 66MHz6

•Two independent 10/100/1000BASE-T (Gigabit) RJ-45 Ethernet interfaces on the main logic board

•Two 1.2MHz HyperTransport interconnects with the following throughput:

–Up to 4.8GB/s (2.4GB/s each way) between system controller and PCI-X

–Up to1.6GB/s (800MB/s each way) between system controller and I/O controller

•Two FireWire 800 ports on back panel and one FireWire 400 port on front panel; 15W total power

•Two USB 2.0 ports (480Mb/s each)

•One DB-9 serial port (RS-232)