Sun Microsystems S16A DMA Registers, Current DMA Address Registers, Next DMA Address Registers

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Registers

S16A User’s Guide

DMA Registers

The S16A provides four independent DMA channels: one each for input and output for each of the two analog I/O channels. Each DMA channel can be accessed to set up a new DMA transfer while it is currently performing a DMA transfer. When the current transfer completes the new one begins automatically without pause, allowing non-stop I/O on both I/O channels in both directions.

The following table shows the assignment of DMA channels to I/O channels.

DMA Channel

Use

 

 

 

 

 

0

Analog I/O channel 0 Input

 

 

 

1

Analog I/O channel 1

Input

 

 

 

2

Analog I/O channel 0

Output

 

 

 

3

Analog I/O channel 1

Output

 

 

 

Table 6. DMA Channel Assignments

Current DMA Address Registers

The Current DMA Address registers are 32-bit read-only registers at addresses 0x40000, 0x40010, 0x40020, and 0x40030, one for each DMA channel. The second-lowest hexadecimal address digit specifies the DMA channel.

These registers hold the address of the DMA currently in progress for each channel. When the current DMA transfer on a channel completes, if there is a “next” one set up, the contents of the Next DMA Address register for the channel are copied to the Current DMA Address register, the next count is copied to the Current DMA Count register, and the new transfer is started automatically.

Bit

Description

 

 

 

 

31–20

The 1 MB page addressed by the DMA.

 

 

19–2

When read, the next address to access on the SBus.

 

 

1–0

Always 0. S16A DMA transfers must be 32-bit word-aligned.

 

 

Table 7. Current DMA Address Registers

Next DMA Address Registers

The Next DMA Address registers are 32-bit registers at addresses 0x40004, 0x40014, 0x40024, and 0x40034, one for each DMA channel. The second-lowest hexadecimal address digit specifies the DMA channel.

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EDT, Inc. October, 1996

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Contents S16A EDT, Inc. October Contents Tables Overview Installation Installing the HardwareInstalling the Software Using SunOS VersionS16A User’s Guide Installation Using System V Release 4 Solaris 2.4 or Later Building the Sample ProgramsIncluded Files ReadmeInput and Output Elements of S16A ApplicationsGeneral DMA Library Routines DMA Library RoutinesRoutine Description S16abufferaddresses S16A-specific Library RoutinesSyntax ArgumentsS16achecknextbuffer S16acancelS16acancelcurrent S16aclose S16aconfigureringbuffers ArgumentsS16adone S16agetdaccontrolregS16agetdiodatareg S16agetdiodirectionregS16agetoutputbits S16aopenS16aread S16aserialreadS16aserialstr S16aserialwriteS16asetdefaults S16asetdaccontrolregS16asetdiodatareg S16asetdiodirectionregS16asetoutputbits S16astartbuffersS16astopbuffers S16awaitforbufferS16awaitfornextbuffer S16awriteError Codes and Conditions Error ConditionsFoiparityerror Hardware Interface Electrical InterfaceS16A Interface Signals Interface SignalsSignal S16A I/O Description Connector Pinout Connector PinoutPin Signal Registers SBus Addresses S16A ROMNext DMA Address Registers DMA RegistersCurrent DMA Address Registers Current Count Registers Control and Next Count RegistersDirect I/O Registers DAC Output Control RegisterDIO Direction Register DIO Data RegisterAnalog Input Module Internal Registers DAC Output Control RegisterName Description Analog Input Module Internal RegistersInput Configuration Registers Input Clock Prescale RegistersTrim Registers Input Gain High Byte ValuesTrim Register Use Trim Registers Trim Output Offset RegistersTemperature Register Analog Input Module Uart RegistersAnalog Input Module Control Protocol Trim Input Gain RegistersWrite to an Input Configuration Register Read from an Input Configuration RegisterWrite to a Clock Prescale Register Read from a Clock Prescale RegisterUart Command/Status Register Read the Temperature RegisterUart Command/Status Register Write to a Trim RegisterXilinx Programming Registers Uart Data RegisterSpecifications References Contacting EDT Index 15-16Configuration ROM
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