Sun Microsystems S16A manual Current Count Registers, Control and Next Count Registers

Page 33

S16A User’s Guide

Registers

These registers hold the address of the next DMA transfer to be performed for each channel. When the current DMA transfer on a channel completes, if there is a “next” one set up, the contents of the Next DMA Address register for the channel are copied to the Current DMA Address register, the next count is copied to the Current DMA Count register, and the new transfer is started automatically.

Bit

Description

 

 

 

 

31–20

Show or store the 1 MB page addressed by the next DMA.

 

 

19–2

Show or store the address within the page for next DMA to use.

 

 

1–0

Set to 0. S16A DMA transfers must be 32-bit word-aligned.

 

 

Table 8. Next DMA Address Registers

Current Count Registers

The Current Count registers are 32-bit read-only registers at address 0x40008, 0x40018, 0x40028, and 0x40038, one for each channel. The second-lowest hexadecimal address digit specifies the DMA channel. The maximum byte count for a single DMA transfer is 1 MB. Each of these registers reflects the counter for the current DMA transfer in progress (if any) on it’s channel.

Bit

Description

 

 

 

 

31–20

Always 0.

 

 

19–2

When read, these bits display how many words remain in the DMA transfer currently in

 

progress.

 

 

1–0

Always 0. S16A DMA transfers consist of whole 32-bit words.

 

 

Table 9. Current Count Registers

Control and Next Count Registers

The Control And Next Count registers are 32-bit registers at address 0x4000C, 0x4001C, 0x4002C, and 0x4003C. The second-lowest hexadecimal address digit specifies the DMA channel. These registers provide the transfer counts and control of the DMA hardware for each of the four DMA channels.

Bit

S16A_

 

Description

 

 

 

 

 

 

 

 

31

INT

 

A read-only status bit. A value of 1 indicates the S16A is asserting an SBus

 

 

 

interrupt.

 

 

 

 

30

 

 

Unused. 0 when read.

 

 

 

 

29

DMA_START

 

A value of 1 enables DMA transfer.

 

 

 

 

28

 

 

Unused. 0 when read.

 

 

 

 

27

EN_EODMA

 

A value of 1 enables end-of-DMA interrupt.

 

 

 

 

26

 

 

Unused. 0 when read.

 

 

 

 

25

DMA_DIR_READ

 

DMA direction: a value of 1 reads host memory, 0 writes it. For channels 0

 

 

 

& 1 must be 0; for channels 2 & 3 must be 1.

 

 

 

 

 

 

Table 10. Control and Next Count Registers

EDT, Inc. October, 1996

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Contents S16A EDT, Inc. October Contents Tables Overview Installing the Hardware InstallationInstalling the Software Using SunOS VersionS16A User’s Guide Installation Building the Sample Programs Using System V Release 4 Solaris 2.4 or LaterReadme Included FilesElements of S16A Applications Input and OutputDMA Library Routines Routine DescriptionGeneral DMA Library Routines S16A-specific Library Routines S16abufferaddressesSyntax ArgumentsS16acancel S16acancelcurrentS16achecknextbuffer S16aclose Arguments S16aconfigureringbuffersS16agetdaccontrolreg S16adoneS16agetdiodirectionreg S16agetdiodataregS16aopen S16agetoutputbitsS16aserialread S16areadS16aserialwrite S16aserialstrS16asetdaccontrolreg S16asetdefaultsS16asetdiodirectionreg S16asetdiodataregS16astartbuffers S16asetoutputbitsS16awaitforbuffer S16astopbuffersS16awrite S16awaitfornextbufferError Conditions FoiparityerrorError Codes and Conditions Electrical Interface Hardware InterfaceInterface Signals Signal S16A I/O DescriptionS16A Interface Signals Connector Pinout Pin SignalConnector Pinout Registers S16A ROM SBus AddressesDMA Registers Current DMA Address RegistersNext DMA Address Registers Control and Next Count Registers Current Count RegistersDAC Output Control Register Direct I/O RegistersDIO Direction Register DIO Data RegisterDAC Output Control Register Analog Input Module Internal RegistersName Description Analog Input Module Internal RegistersInput Clock Prescale Registers Input Configuration RegistersInput Gain High Byte Values Trim RegistersTrim Register Use Trim Registers Trim Output Offset RegistersAnalog Input Module Uart Registers Temperature RegisterAnalog Input Module Control Protocol Trim Input Gain RegistersRead from an Input Configuration Register Write to an Input Configuration RegisterWrite to a Clock Prescale Register Read from a Clock Prescale RegisterRead the Temperature Register Uart Command/Status RegisterUart Command/Status Register Write to a Trim RegisterUart Data Register Xilinx Programming RegistersSpecifications References Contacting EDT 15-16 IndexConfiguration ROM
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