Sun Microsystems S16A manual Trim Registers, Input Gain High Byte Values, Trim Register Use

Page 37

S16A User’s Guide

 

Registers

 

 

 

 

 

 

 

Value (hex)

 

AIN_

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

08xx

 

X1

Unit gain.

 

 

 

 

 

 

 

 

09xx

 

X2

Gain factor 2.

 

 

 

 

 

 

 

 

0Axx

 

X5

Gain factor 5.

 

 

 

 

 

 

 

 

0Cxx

 

X10_1

First gain factor 10. Uses the first-stage gain at maximum.

 

 

 

 

 

 

 

 

10xx

 

X10_2

Second gain factor 10. Uses the second-stage 10 x gain.

 

 

 

Recommended for higher bandwidth.

 

 

 

 

 

 

 

 

 

 

 

 

 

11xx

 

X20

Gain factor 20.

 

 

 

 

 

 

 

 

12xx

 

X50

Gain factor 50.

 

 

 

 

 

 

 

 

14xx

 

X100

Gain factor 100. Uses both stages at maximum.

 

 

 

 

 

 

 

Table 14. Input Gain (High Byte) Values

Trim Registers

The Analog Input Module contains six Digital-to-Analog converters (DACs) that control various trim adjustments on the S16A. The analog input and output signals can be level-shifted, and the input signal gains can be fine-tuned with these DACs. These trim DACs are controlled by six 8-bit trim registers. These trim registers are set with the D command, described in Analog Input Module Control Protocol beginning on page 34.

As Analog Input Module registers, these registers are accessed via the UART registers.

Trim Register

Use

 

 

 

 

2

controls the output trim for analog I/O channel 0

 

 

3

controls the output trim for analog I/O channel 1

 

 

4

controls the input gain trim for analog I/O channel 0

 

 

5

controls the input offset for analog I/O channel 0

 

 

6

controls the input gain trim for analog I/O channel 1

 

 

7

controls the input offset for analog I/O channel 1

 

 

Table 15. Trim Registers

Trim Output Offset Registers

These two trim registers control a voltage offset for the output of each analog I/O channel. Trim register 2 controls the output trim for analog I/O channel 0; trim register 3 controls the output trim for channel 1.

The recommended procedure for adjusting these output trim registers is to first adjust one of the analog I/O channels’ input offset to be zero-calibrated by configuring its input to be ground and adjusting its input offset while monitoring the input data for zero. After setting up one of the analog I/O channels as a calibrated input, reconfigure the analog I/O channel input to monitor the analog I/O channel output in question. Finally, with all zeros for the output data, adjust the output trim until zeros are read in the input channel.

EDT, Inc. October, 1996

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Contents S16A EDT, Inc. October Contents Tables Overview Installing the Hardware InstallationInstalling the Software Using SunOS VersionS16A User’s Guide Installation Building the Sample Programs Using System V Release 4 Solaris 2.4 or LaterReadme Included FilesElements of S16A Applications Input and OutputRoutine Description DMA Library RoutinesGeneral DMA Library Routines S16A-specific Library Routines S16abufferaddressesSyntax ArgumentsS16acancelcurrent S16acancelS16achecknextbuffer S16aclose Arguments S16aconfigureringbuffersS16agetdaccontrolreg S16adoneS16agetdiodirectionreg S16agetdiodataregS16aopen S16agetoutputbitsS16aserialread S16areadS16aserialwrite S16aserialstrS16asetdaccontrolreg S16asetdefaultsS16asetdiodirectionreg S16asetdiodataregS16astartbuffers S16asetoutputbitsS16awaitforbuffer S16astopbuffersS16awrite S16awaitfornextbufferFoiparityerror Error ConditionsError Codes and Conditions Electrical Interface Hardware InterfaceSignal S16A I/O Description Interface SignalsS16A Interface Signals Pin Signal Connector PinoutConnector Pinout Registers S16A ROM SBus AddressesCurrent DMA Address Registers DMA RegistersNext DMA Address Registers Control and Next Count Registers Current Count RegistersDAC Output Control Register Direct I/O RegistersDIO Direction Register DIO Data RegisterDAC Output Control Register Analog Input Module Internal RegistersName Description Analog Input Module Internal RegistersInput Clock Prescale Registers Input Configuration RegistersInput Gain High Byte Values Trim RegistersTrim Register Use Trim Registers Trim Output Offset RegistersAnalog Input Module Uart Registers Temperature RegisterAnalog Input Module Control Protocol Trim Input Gain RegistersRead from an Input Configuration Register Write to an Input Configuration RegisterWrite to a Clock Prescale Register Read from a Clock Prescale RegisterRead the Temperature Register Uart Command/Status RegisterUart Command/Status Register Write to a Trim RegisterUart Data Register Xilinx Programming RegistersSpecifications References Contacting EDT 15-16 IndexConfiguration ROM
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