Quatech MPAP-100 user manual FIFO status and control, Interrupt status

10.4 FIFO status and control

Several registers are used to control the FIFOs and monitor their status. These registers are detailed in other chapters of this manual.

10.4.1 Interrupt status

Three interrupt statuses, listed in Table 8, can be generated by four events related to FIFO activity. In each case, a latched bit in the Interrupt Status Register is set to a logic 1 (see page

43). These bits are write-clear, meaning that software must write a 1 to a bit in order to clear it.

IMPORTANT

FIFO-related interrupts will occur only when the MPAP-100 interrupt source is set to INTSCC. See Table 10 on page 41 for details.

Event	Interrupt Status	Comment
	Register Bit
Transmit FIFO drained	TX_FIFO	Software can write at least
		512 bytes to the transmit
past the half-full mark	(bit 1)
		FIFO.
Receive FIFO filled past		Software can read at least
		512 bytes from the receive
the half-full mark
	RX_FIFO	FIFO.
Receive data timeout with	(bit 2)	Software can read bytes
		from the receive FIFO until
non-empty FIFO
		the FIFO is empty.
Special receive pattern	RX_PAT	Software can read data
		from the receive FIFO as
detected	(bit 3)
		desired.
Table 8 --- FIFO-related interrupt statuses

IMPORTANT

Software can differentiate between the two types of RX_FIFO interrupts by examining the RXH bit in the FIFO Status Register. If RXH is clear (logic 0), the interrupt occurred because of a timeout.