Quatech MPAP-100 user manual SYNCA pin, RING pin

Page 55

19.1 SYNCA (pin 10)

	N/C 13		25	TM (OUTPUT)
	N/C	12
			24	TxCLK (DTE)
	RxCLK (DTE)11
			23	N/C
	SYNCA	10
			22	RING
	N/C 9
			21	RLBK (OUTPUT)
	CD	8
	DGND	7	20	DTR
			19	N/C
	DSR	6
			18	LLBK (OUTPUT)
	CTS	5
			17	RxCLK (DCE)
	RTS	4
			16	N/C
	RxD	3
			15	TxCLK (DCE)
	TxD	2
	CGND	1	14	N/C

Figure 2 --- MPAP-100 Output Connector

The testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback (RL). These signals are asserted with certain bits in the Communications Register. When a Test Mode (TM) condition is received from the DCE, an interrupt can optionally be generated.

19.1 SYNCA (pin 10)

If EXTSYNC (bit 6) in the Communications Register is set to a logic 1, the SYNCA signal from the connector is used to drive the active-low SYNC input of SCC channel A. The signal is inverted by the RS-232 receiver, so a positive voltage on pin 10 will assert SYNCA. The SCC must be specifically programmed to recognize external synchronization.

19.2 RING (pin 22)

If Card and Socket Services has set the SIGCHG bit in the PCMCIA Configuration Status Register to a logic 1, the RING signal is routed to the STSCHG line on the PCMCIA bus. The signal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG.

Table 17 shows the pin configuration of the MPAP-100 DTE connector. The definitions of the interchange circuits according to the RS-232-D standard can be found starting on page 52.

Pin

To

DTE

From

DTE

Signal

RS-232-D

Circuit

SCC Pin or Register Bit

Image 55

Contents QUATECH, INC MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTERUsers Manual for PCMCIA Card Standard compatible machinesSynchronous Communications Adapter WARRANTY INFORMATIONMPAP-100 PRODUCT DESCRIPTION Single Channel PCMCIA RS-232-DCopyright 2001 Quatech, Inc Table of Contents 5.2.1 Tying a configuration to a particular socket5.3 OS/2 Client Driver Configuration Examples 5.4 Monitoring The Status Of PCMCIA Cards22.1.4 Older Versions of Card and Socket Services Table of Contents10.3.1 Using channel A for both transmit and receive Accessing the SCC while FIFOs are enabled1.1 System Requirements 1 Introduction2 Hardware Installation 3 DOS / Windows 3.x Software Installation 3.1 MPAP-100 Client Driver for DOS 3.1.1 DOS client driver installationDEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.3 Hot Swapping 3.1.2 Auto Fallback configurationPage DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5 3.2 DOS Client Driver examplesDEVICE=C\MPAP-100\MPAP1CL.SYS DEVICE=C\MPAP-100\MPAP1CL.SYS b300,c3.3.2 Hot Swapping is not supported 3.3 MPAP-100 Enabler for DOS3.3.1 DOS Enabler Installation 3.3.3 Configuring a cardMPAP1EN S#,B#,I#,W#,C MPAP1EN S#,R,W# 3.3.4 Releasing a cards configurationMPAP1EN.EXE s0,r 3.4 DOS Enabler ExamplesMPAP1EN.EXE s0,b300,i5,c MPAP1EN.EXE s1,b300,i3,wd84.1 Using the Add New Hardware Wizard 4 Windows 95/98 InstallationPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C 5 OS/2 Software Installation5.2 OS/2 Client Driver Installation 5.1 System Requirements5.2.3 Hot Swapping 5.2.2 Auto Fallback configurationDEVICE=C\MPAP-100\MPAP100.SYS 300,5 5.5 Installing OS/2 PCMCIA SupportPage 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts Asynchronous Communications 9 SCC General InformationSDLC/HDLC Bit Synchronous Communications Byte-oriented Synchronous Communications9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A Interrupt vector Master interrupt control and resetcoding, CRC reset Interrupt control, Wait/DMA request controlClockFrequency TimeConst 2 BaudRate ClockMode 9.2 Baud Rate Generator Programming9.3 SCC Data Encoding Methods 9.4 Support for SCC Channel B9.4.3 Extra handshaking for channel A 9.4.1 Receive data and clock signals9.4.4 Other signals are not used 9.4.2 Extra clock support for channel A9.5.1 Register Pointer Bits 9.5 SCC Incompatibility Warnings9.5.2 Software Interrupt Acknowledge 10.2.1 Transmit FIFO 10.2 Accessing the FIFOs10 FIFO Operation 10.1 Enabling and disabling the FIFOs10.2.2 Receive FIFO 10.3 SCC configuration for FIFO operationRegister 10.3.2 Using channel B for receive 10.4.1 Interrupt status 10.4 FIFO status and control10.4.4 Controlling the FIFOs 10.4.2 Resetting the FIFOs10.5 Accessing the SCC while FIFOs are enabled 10.4.3 Reading current FIFO statusPage 10.7 Receive FIFO timeout SWSYNC 11 Communications RegisterBit 2 TCKEN --- Transmit Clock Source RCKEN --- Receive Clock SourceBits 1-0 Reserved, always External Data FIFOs Present --- Reserved, always 12 Configuration RegisterINTS1, INTS0 --- Interrupt Source and Enable Bits FIFOEN --- External data FIFO enableRXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register Bits 7-0 Receive Pattern CharacterThis is 16 Receive Pattern Character RegisterBits 7-0 Receive Pattern Count 17 Receive Pattern Count RegisterBit 6 Reserved, always Bits 5-0 Timeout Interval 18 Receive FIFO Timeout RegisterBit 7 X16MODE --- Clock Mode 19 External Connections 19.2 RING pin 19.1 SYNCA pin19.3 Null-modem cables CIRCUIT CB - CLEAR TO SEND 20 DTE Interface SignalsCIRCUIT AB - SIGNAL GROUND CIRCUIT BB - RECEIVED DATACIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSRCIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR CIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RINGCIRCUIT TM - TEST MODE 21 Specifications 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers 22 Software Troubleshooting22.1.3 Multiple Configuration Attempts 22.2 DOS Enabler22.3 OS/2 Client Driver 22.3.1 Resources Not Available 22.2.1 With Card and Socket Services22.2.2 Socket Numbers 22.2.3 Memory range exclusionPage MPAP-100 Users Manual Revision March P/N