Quatech MPAP-100 Circuit Cc - Dce Ready Data Set Ready Connector Notation Dsr, DIRECTION From DCE

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CIRCUIT CC - DCE READY (DATA SET READY)

CONNECTOR NOTATION: DSR

DIRECTION: From DCE

This signal indicates the status of the local DCE by reporting to the DTE device that a communication channel has been established.

CIRCUIT CD - DTE READY (DATA TERMINAL READY)

CONNECTOR NOTATION: DTR

DIRECTION: To DCE

This signal controls the switching of the DCE to the communication channel. The DTE will generate this signal to prepare the DCE to be connected to or removed from the communication channel.

CIRCUIT CE - RING INDICATOR

CONNECTOR NOTATION: RING

DIRECTION: From DCE

This signal indicates that a ringing signal is being received on the communication channel.

CIRCUIT CF - RECEIVED LINE SIGNAL DETECT (CARRIER DETECT)

CONNECTOR NOTATION: CD

DIRECTION: From DCE

This signal indicates to the DTE whether the DCE is conditioned to receive data from the communication channel, but does not indicate the relative quality of the data signals being received.

CIRCUIT DA - TRANSMIT SIGNAL ELEMENT TIMING (DTE SOURCE)

CONNECTOR NOTATION: TXCLK (DTE)

DIRECTION: To DCE

This signal, generated by the DTE, provides the DCE with element timing information pertaining to the data transmitted by the DTE. The DCE can use this information for its received data.

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Contents for PCMCIA Card Standard compatible machines MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTERUsers Manual QUATECH, INCPRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D WARRANTY INFORMATIONMPAP-100 Synchronous Communications AdapterCopyright 2001 Quatech, Inc 5.4 Monitoring The Status Of PCMCIA Cards 5.2.1 Tying a configuration to a particular socket5.3 OS/2 Client Driver Configuration Examples Table of ContentsAccessing the SCC while FIFOs are enabled Table of Contents10.3.1 Using channel A for both transmit and receive 22.1.4 Older Versions of Card and Socket Services1 Introduction 1.1 System Requirements2 Hardware Installation 3 DOS / Windows 3.x Software Installation 3.1 MPAP-100 Client Driver for DOS 3.1.1 DOS client driver installationDEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C 3.1.2 Auto Fallback configuration 3.1.3 Hot SwappingPage DEVICE=C\MPAP-100\MPAP1CL.SYS b300,c 3.2 DOS Client Driver examplesDEVICE=C\MPAP-100\MPAP1CL.SYS DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i53.3.3 Configuring a card 3.3 MPAP-100 Enabler for DOS3.3.1 DOS Enabler Installation 3.3.2 Hot Swapping is not supportedMPAP1EN S#,B#,I#,W#,C 3.3.4 Releasing a cards configuration MPAP1EN S#,R,W#MPAP1EN.EXE s1,b300,i3,wd8 3.4 DOS Enabler ExamplesMPAP1EN.EXE s0,b300,i5,c MPAP1EN.EXE s0,r4 Windows 95/98 Installation 4.1 Using the Add New Hardware WizardPage Page 4.2 Viewing Resources with Device Manager 4.3 Configuration Options 5.1 System Requirements 5 OS/2 Software Installation5.2 OS/2 Client Driver Installation DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C5.2.2 Auto Fallback configuration 5.2.3 Hot Swapping5.5 Installing OS/2 PCMCIA Support DEVICE=C\MPAP-100\MPAP100.SYS 300,5Page 6 Using the MPAP-100 with Syncdrive 7 Addressing 8 Interrupts Byte-oriented Synchronous Communications 9 SCC General InformationSDLC/HDLC Bit Synchronous Communications Asynchronous Communications9.1 Accessing the registers Example 3 Write data into the transmit buffer of channel A Interrupt control, Wait/DMA request control Master interrupt control and resetcoding, CRC reset Interrupt vector9.4 Support for SCC Channel B 9.2 Baud Rate Generator Programming9.3 SCC Data Encoding Methods ClockFrequency TimeConst 2 BaudRate ClockMode9.4.2 Extra clock support for channel A 9.4.1 Receive data and clock signals9.4.4 Other signals are not used 9.4.3 Extra handshaking for channel A9.5.1 Register Pointer Bits 9.5 SCC Incompatibility Warnings9.5.2 Software Interrupt Acknowledge 10.1 Enabling and disabling the FIFOs 10.2 Accessing the FIFOs10 FIFO Operation 10.2.1 Transmit FIFO10.3 SCC configuration for FIFO operation 10.2.2 Receive FIFORegister 10.3.2 Using channel B for receive 10.4 FIFO status and control 10.4.1 Interrupt status10.4.3 Reading current FIFO status 10.4.2 Resetting the FIFOs10.5 Accessing the SCC while FIFOs are enabled 10.4.4 Controlling the FIFOsPage 10.7 Receive FIFO timeout 11 Communications Register SWSYNCBit 2 TCKEN --- Transmit Clock Source RCKEN --- Receive Clock SourceBits 1-0 Reserved, always FIFOEN --- External data FIFO enable 12 Configuration RegisterINTS1, INTS0 --- Interrupt Source and Enable Bits External Data FIFOs Present --- Reserved, alwaysRXSRC --- Receive FIFO DMA Source 13 Interrupt Status Register 14 FIFO Status Register 15 FIFO Control Register 16 Receive Pattern Character Register Bits 7-0 Receive Pattern CharacterThis is17 Receive Pattern Count Register Bits 7-0 Receive Pattern CountBit 6 Reserved, always Bits 5-0 Timeout Interval 18 Receive FIFO Timeout RegisterBit 7 X16MODE --- Clock Mode 19 External Connections 19.1 SYNCA pin 19.2 RING pin19.3 Null-modem cables CIRCUIT BB - RECEIVED DATA 20 DTE Interface SignalsCIRCUIT AB - SIGNAL GROUND CIRCUIT CB - CLEAR TO SENDCIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSRCIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECTCIRCUIT TM - TEST MODE 21 Specifications 22.2 DOS Enabler 22 Software Troubleshooting22.1.3 Multiple Configuration Attempts 22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers22.2.3 Memory range exclusion 22.2.1 With Card and Socket Services22.2.2 Socket Numbers 22.3 OS/2 Client Driver 22.3.1 Resources Not AvailablePage MPAP-100 Users Manual Revision March P/N