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The MPAP-100 is a single-channel device. Portions of SCC channel B are used to augment channel A. Channel B cannot be used for transmit, but may be used for receive, subject to certain limitations.
9.4.1Receive data and clock signals
The receive data signals RXDA and RXDB are tied together. The receive clock input signals RTxCA and RTxCB are also tied together. This can be useful in unusual applications. It would be possible to run the receiver and transmitter at different baud rates, using channel B's baud rate generator and receiver for the received data. Of course, the channel A transmitter and receiver can be run at different speeds simply by having external data clocks supplied to TRxCA and RTxCA from the cable.
The W/REQB signal is used to generate DMA requests between the SCC and the external FIFOs if channel B is used for receive.
9.4.2Extra clock support for channel A
The TRxCB clock output can be routed back to RTxCA as another way to use the channel B baud rate generator to derive an independent clock for the channel A receiver. This is controlled by the RCKEN bit in the Communications Register (see page 39).
9.4.3Extra handshaking for channel A
The SCC does not provide a DSR input for either channel. The MPAP-100 routes the DSR signal from the connector to the DCDB input of the SCC. Software can therefore use DCDB as a surrogate for DSR on channel A.
9.4.4Other signals are not used
All channel B signals not listed above are not available at the connector. The CTSB and SYNCB inputs are tied to their inactive states. The TXDB, DTR/REQB, and RTSB outputs are left open.
Contents
for PCMCIA Card Standard compatible machines
MPAP-100 RS-232 PCMCIA SYNCHRONOUS ADAPTER
Users Manual
QUATECH, INC
PRODUCT DESCRIPTION Single Channel PCMCIA RS-232-D
WARRANTY INFORMATION
MPAP-100
Synchronous Communications Adapter
Copyright 2001 Quatech, Inc
5.4 Monitoring The Status Of PCMCIA Cards
5.2.1 Tying a configuration to a particular socket
5.3 OS/2 Client Driver Configuration Examples
Table of Contents
Accessing the SCC while FIFOs are enabled
Table of Contents
10.3.1 Using channel A for both transmit and receive
22.1.4 Older Versions of Card and Socket Services
1 Introduction
1.1 System Requirements
2 Hardware Installation
3 DOS / Windows 3.x Software Installation
3.1 MPAP-100 Client Driver for DOS
3.1.1 DOS client driver installation
DEVICE=drive\path\MPAP1CL.SYS S#,B#,I#,C ... S#,B#,I#,C
3.1.2 Auto Fallback configuration
3.1.3 Hot Swapping
Page
DEVICE=C\MPAP-100\MPAP1CL.SYS b300,c
3.2 DOS Client Driver examples
DEVICE=C\MPAP-100\MPAP1CL.SYS
DEVICE=C\MPAP-100\MPAP1CL.SYS s0,b300,i5
3.3.3 Configuring a card
3.3 MPAP-100 Enabler for DOS
3.3.1 DOS Enabler Installation
3.3.2 Hot Swapping is not supported
MPAP1EN S#,B#,I#,W#,C
3.3.4 Releasing a cards configuration
MPAP1EN S#,R,W#
MPAP1EN.EXE s1,b300,i3,wd8
3.4 DOS Enabler Examples
MPAP1EN.EXE s0,b300,i5,c
MPAP1EN.EXE s0,r
4 Windows 95/98 Installation
4.1 Using the Add New Hardware Wizard
Page
Page
4.2 Viewing Resources with Device Manager
4.3 Configuration Options
5.1 System Requirements
5 OS/2 Software Installation
5.2 OS/2 Client Driver Installation
DEVICE=drive\path\MPAP100.SYS addr,irq,C ... addr,irq,C
5.2.2 Auto Fallback configuration
5.2.3 Hot Swapping
5.5 Installing OS/2 PCMCIA Support
DEVICE=C\MPAP-100\MPAP100.SYS 300,5
Page
6 Using the MPAP-100 with Syncdrive
7 Addressing
8 Interrupts
Byte-oriented Synchronous Communications
9 SCC General Information
SDLC/HDLC Bit Synchronous Communications
Asynchronous Communications
9.1 Accessing the registers
Example 3 Write data into the transmit buffer of channel A
Interrupt control, Wait/DMA request control
Master interrupt control and reset
coding, CRC reset
Interrupt vector
9.4 Support for SCC Channel B
9.2 Baud Rate Generator Programming
9.3 SCC Data Encoding Methods
ClockFrequency TimeConst 2 BaudRate ClockMode
9.4.2 Extra clock support for channel A
9.4.1 Receive data and clock signals
9.4.4 Other signals are not used
9.4.3 Extra handshaking for channel A
9.5.1 Register Pointer Bits
9.5 SCC Incompatibility Warnings
9.5.2 Software Interrupt Acknowledge
10.1 Enabling and disabling the FIFOs
10.2 Accessing the FIFOs
10 FIFO Operation
10.2.1 Transmit FIFO
10.3 SCC configuration for FIFO operation
10.2.2 Receive FIFO
Register
10.3.2 Using channel B for receive
10.4 FIFO status and control
10.4.1 Interrupt status
10.4.3 Reading current FIFO status
10.4.2 Resetting the FIFOs
10.5 Accessing the SCC while FIFOs are enabled
10.4.4 Controlling the FIFOs
Page
10.7 Receive FIFO timeout
11 Communications Register
SWSYNC
Bit 2 TCKEN --- Transmit Clock Source
RCKEN --- Receive Clock Source
Bits 1-0 Reserved, always
FIFOEN --- External data FIFO enable
12 Configuration Register
INTS1, INTS0 --- Interrupt Source and Enable Bits
External Data FIFOs Present --- Reserved, always
RXSRC --- Receive FIFO DMA Source
13 Interrupt Status Register
14 FIFO Status Register
15 FIFO Control Register
16 Receive Pattern Character Register
Bits 7-0 Receive Pattern CharacterThis is
17 Receive Pattern Count Register
Bits 7-0 Receive Pattern Count
Bit 6 Reserved, always Bits 5-0 Timeout Interval
18 Receive FIFO Timeout Register
Bit 7 X16MODE --- Clock Mode
19 External Connections
19.1 SYNCA pin
19.2 RING pin
19.3 Null-modem cables
CIRCUIT BB - RECEIVED DATA
20 DTE Interface Signals
CIRCUIT AB - SIGNAL GROUND
CIRCUIT CB - CLEAR TO SEND
CIRCUIT CE - RING INDICATOR CONNECTOR NOTATION RING
CIRCUIT CC - DCE READY DATA SET READY CONNECTOR NOTATION DSR
CIRCUIT CD - DTE READY DATA TERMINAL READY CONNECTOR NOTATION DTR
CIRCUIT CF - RECEIVED LINE SIGNAL DETECT CARRIER DETECT
CIRCUIT TM - TEST MODE
21 Specifications
22.2 DOS Enabler
22 Software Troubleshooting
22.1.3 Multiple Configuration Attempts
22.1 DOS Client Driver 22.1.1 Generic SuperClient Drivers
22.2.3 Memory range exclusion
22.2.1 With Card and Socket Services
22.2.2 Socket Numbers
22.3 OS/2 Client Driver 22.3.1 Resources Not Available
Page
MPAP-100 Users Manual Revision March P/N