Texas Instruments SLVP089 manual Design Procedures, Duty Cycle Estimate

Design Procedures

2.3 Design Procedures

Detailed steps in the design of a buck-mode converter may be found in Designing With the TL5001C PWM Controller (literature number SLVA034) from TI. This section shows the basic steps involved in this design.

2.3.1Duty Cycle Estimate

The duty cycle for a continuous-mode step-down converter is approximately:

D +VO )Vd

VI – VSAT

Assuming the diode or synchronous switch forward voltage Vd = 0.12 V and

the power-switch-on voltage VSAT = 0.15 V, the duty cycle for VI = 5.5, 9, and 12 V is 0.64, 0.39, and 0.29, respectively.

2.3.2Output Filter

A synchronous buck converter uses a single-stage LC filter. Choose an induc- tor to maintain continuous-mode operation down to 15 percent of the rated out- putDload:

IO +2		0.15 IO +2		0.15		3 +0.9 A
The inductor value is:
L +	￿VI – VSAT –DVO￿		D	t
		IO
+
(12 – 0.15 – 3.3)			0.29		￿10	10–6￿
							+27.6 mH
			0.9

Assuming that all of the inductor ripple current flows through the capacitor and the effective series resistance (ESR) is zero, the capacitance needed is:

C +		DIO	￿+		0.9	+22.5 mF
	8 f	￿D		8	￿100 103￿ 0.05
			VO

Assuming the capacitance is very large, the ESR needed to limit the ripple to

50 mV is:

ESR +DDVO +0.05 +0.056 W

IO 0.9

The output filter capacitor should be rated at least ten times the calculated ca- pacitance and 30–50 percent lower than the calculated ESR. This design used two 100-mF capacitors in parallel with a multilayer ceramic to reduce ESR.

2.3.3Power Switch

Based on the preliminary estimate, rDS(ON) should be less than 0.015 V ￿3A = 50 mW. The IRF7406 is a 30-V p-channel MOSFET with rDS(ON) = 40 mW.

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