Texas Instruments SLVP089 manual Bode Plot

Page 27

Design Procedures

Figure 2–3 shows the bode plot for the compensation network.

Figure 2–3. Bode Plot

 

45

 

 

 

90

 

 

40

 

 

 

70

 

 

35

 

 

 

50

Phase – Degrees (Dashed)

Gain – dB (Solid)

30

 

 

 

30

25

 

 

 

10

20

 

 

 

–10

15

 

 

 

–30

10

 

 

 

–50

 

 

 

 

 

 

5

 

 

 

–70

 

 

0

102

103

104

–90

 

 

10

105

 

Frequency – Hz

Note from the output response shown in Figure 2–4 that the minimum phase margin is 40 degrees and the bandwidth is 18 kHz under nominal operating conditions.

Figure 2–4. Output Response

OUTPUT RESPONSE

 

70

 

 

 

–180

 

 

60

 

 

 

 

 

 

50

 

 

 

–225

Phase – Degrees (Dashed)

 

 

 

 

 

Gain – dB (Solid)

40

 

 

 

 

30

 

 

 

 

 

 

 

 

–270

20

 

 

 

 

10

 

 

 

 

0

 

 

 

–315

 

 

 

 

 

 

 

 

 

 

 

 

–10

 

 

 

 

 

 

–20

102

103

104

–360

 

 

10

105

 

Frequency – Hz

Design Procedure

2-9

Image 27
Contents User’s Guide 07/98 Literature Number SLVU001A July Important Notice About This Manual Read This FirstTrademarks Contents Tables FiguresTopic HardwareTypical Synchronous Buck Converter IntroductionSchematic Diagram SchematicInput/Output Connections Power SupplyShows the SLVP089 board layout Board LayoutBill of Materials Bill of MaterialsLoad Regulation and Ripple, 3.3-V 9-V Input Test ResultsPower Switch Turn-On and Delay from Q2 Off Inductor and Output Ripple Page Design Procedure Introduction Operating Specifications Operating SpecificationsDuty Cycle Estimate Design Procedures+ 3 W Controller Functions + DD V O Compensation Network Bode Plot