Texas Instruments SLVP089 manual + 3 W

Design Procedures

The power dissipation (conduction + switching losses) can be approximated as:

P	D	+￿I2	r	DS(ON)	D ￿)￿0.5 V	I	I	O	t	r)f	f ￿
		O

Assuming total switching time, tr+f, = 100 ns, a 55° C maximum ambient tem- perature, and rDS(ON) adjustment factor = 1.6, then:

P	D	+)￿32	(0.04	1.6)	0.64￿
		0.5	5.5	3	￿0.1 10–6￿￿100 103￿￿+0.45 W

The thermal impedance for Q1 RqJA = 90° C/W for FR-4 with 2-oz. copper and a one-inch-square pattern, thus:

TJ +TA )￿RqJA PD￿+55 )(90 0.45) +96° C

2.3.4Synchronous Switch and Rectifier

The synchronous switch calculations follow the same path as the power switch

except that the duty cycle is 1–D. Then rDS(ON) should be less than 0.012 V￿

3A = 40 mW. Selecting an IRF7201 with an rDS(ON) = 30 mW, then:

P	D	)+￿32	(0.03	1.6)	0.36￿
		0.5	5.5	3	0.1 10–6￿￿100	103￿￿+0.238 W
TJ		+TA )￿RqJA		PD￿+55 )(90 0.238)		+76° C

The catch rectifier serves as a backup device for the synchronous switch and conducts during the time interval when both devices are off. The 30BQ015 is a 3-A, 15-V rectifier in an SMC power surface-mount package. If the synchro- nous switch were not used, the power dissipation for the catch diode would be:

PD +IO VD ￿1 – DMin￿+3 0.7 0.71 +1.491 W

However, since the catch diode actually conducts only during the deadtime and switching time, the power dissipation is:

PD +IO	VD	tr)f	f
3	0.7	￿0.1	10–6￿￿100 103￿+2.1 mW

2.3.5Snubber Network

A snubber network is usually needed to suppress the ringing at the node where the power switch drain, output inductor, and synchronous switch drain con- nect. This is usually a trial-and-error sequence of steps to optimize the net- work, but as a starting point, select a snubber capacitor with a value that is 4–10 times larger than the estimated capacitance of the synchronous switch and catch rectifier. Then, measuring a ringing time constant of 3 ns, R is:

R +	3 10–9	+	3	10–9	+3 W
	C		1000	10–12

Design Procedure 2-5