32581C

List of Figures

Figure 7-6.

Capture Video Mode Weave Example Using Two Video Frame Buffers

. . . . . . . 316

Figure 7-7.

Video Block Diagram

. . . . . . . 317

Figure 7-8.

Horizontal Downscaler Block Diagram

. . . . . . . 318

Figure 7-9.

Linear Interpolation Calculation

. . . . . . . 319

Figure 7-10.

Mixer/Blender Block Diagram

. . . . . . . 320

Figure 7-11.

Graphics/Video Frame with Alpha Windows

. . . . . . . 322

Figure 7-12.

Color Key and Alpha Blending Logic

. . . . . . . 324

Figure 7-13.

TFT Power Sequence

. . . . . . . 325

Figure 7-14.

PLL Block Diagram

. . . . . . . 326

Figure 9-1.

Differential Input Sensitivity for Common Mode Range

. . . . . . . 360

Figure 9-2.

Drive level and Measurement Points

. . . . . . . 362

Figure 9-3.

Memory Controller Drive Level and Measurement Points

. . . . . . . 363

Figure 9-4.

Memory Controller Output Valid Timing Diagram

. . . . . . . 365

Figure 9-5.

Read Data In Setup and Hold Timing Diagram

. . . . . . . 365

Figure 9-6.

Video Input Port Timing Diagram

. . . . . . . 366

Figure 9-7.

TFT Timing Diagram

. . . . . . . 367

Figure 9-8.

ACB Signals: Rising Time and Falling Timing Diagram

. . . . . . . 369

Figure 9-9.

ACB Start and Stop Condition Timing Diagram

. . . . . . . 369

Figure 9-10.

ACB Start Condition Timing Diagram

. . . . . . . 370

Figure 9-11.

ACB Data Bit Timing Diagram

. . . . . . . 370

Figure 9-12.

Testing Setup for Slew Rate and Minimum Timing

. . . . . . . 371

Figure 9-13.

V/I Curves for PCI Output Signals

. . . . . . . 372

Figure 9-14.

PCICLK Timing and Measurement Points

. . . . . . . 373

Figure 9-15.

Load Circuits for Maximum Time Measurements

. . . . . . . 374

Figure 9-16.

Output Timing Measurement Conditions

. . . . . . . 375

Figure 9-17.

Input Timing Measurement Conditions

. . . . . . . 376

Figure 9-18.

PCI Reset Timing

. . . . . . . 376

Figure 9-19.

Sub-ISA Read Operation Timing Diagram

. . . . . . . 379

Figure 9-20.

Sub-ISA Write Operation Timing Diagram

. . . . . . . 380

Figure 9-21.

LPC Output Timing Diagram

. . . . . . . 381

Figure 9-22.

LPC Input Timing Diagram

. . . . . . . 381

Figure 9-23.

IDE Reset Timing Diagram

. . . . . . . 382

Figure 9-24.

Register Transfer to/from Device Timing Diagram

. . . . . . . 384

Figure 9-25.

PIO Data Transfer to/from Device Timing Diagram

. . . . . . . 386

Figure 9-26.

Multiword DMA Data Transfer Timing Diagram

. . . . . . . 388

Figure 9-27.

Initiating an UltraDMA Data in Burst Timing Diagram

. . . . . . . 390

Figure 9-28.

Sustained UltraDMA Data In Burst Timing Diagram

. . . . . . . 391

Figure 9-29.

Host Pausing an UltraDMA Data In Burst Timing Diagram

. . . . . . . 392

Figure 9-30.

Device Terminating an UltraDMA Data In Burst Timing Diagram

. . . . . . . 393

Figure 9-31.

Host Terminating an UltraDMA Data In Burst Timing Diagram

. . . . . . . 394

Figure 9-32.

Initiating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 395

Figure 9-33.

Sustained UltraDMA Data Out Burst Timing Diagram

. . . . . . . 396

Figure 9-34.

Device Pausing an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 397

Figure 9-35.

Host Terminating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 398

Figure 9-36.

Device Terminating an UltraDMA Data Out Burst Timing Diagram

. . . . . . . 399

Figure 9-37.

Data Signal Rise and Fall Timing Diagram

. . . . . . . 402

Figure 9-38.

Source Differential Data Jitter Timing Diagram

. . . . . . . 402

Figure 9-39.

EOP Width Timing Diagram

. . . . . . . 403

Figure 9-40.

Receiver Jitter Tolerance Timing Diagram

. . . . . . . 403

Figure 9-41.

UART, Sharp-IR, SIR, and Consumer Remote Control Timing Diagram

. . . . . . . 404

Figure 9-42.

Fast IR (MIR and FIR) Timing Diagram

. . . . . . . 405

Figure 9-43.

Standard Parallel Port Typical Data Exchange Timing Diagram

. . . . . . . 406

Figure 9-44.

Enhanced Parallel Port Timing Diagram

. . . . . . . 407

Figure 9-45.

ECP Forward Mode Timing Diagram

. . . . . . . 408

Figure 9-46.

ECP Reverse Mode Timing Diagram

. . . . . . . 409

6

AMD Geode™ SC3200 Processor Data Book

Page 6
Image 6
AMD SC3200 316, 360, Drive level and Measurement Points 362, 363, 365, 371, 374, 386, 390, 391, 392, 393, 394, 397, 398