Lock#, Devsel#, Bhe#, Serr# | AMD SC3200 manual

Signal Definitions

32581C

3.4.6PCI Bus Interface Signals (Continued)

Signal Name	BalL No.	Type	Description	Mux

LOCK#	H3	I/O	Lock Operation. LOCK# indicates an atomic operation	---
			that may require multiple transactions to complete. When
			LOCK# is asserted, non-exclusive transactions may pro-
			ceed to an address that is not currently locked (at least
			16 bytes must be locked). A grant to start a transaction
			on PCI does not guarantee control of LOCK#. Control of
			LOCK# is obtained under its own protocol in conjunction
			with GNT#.
			It is possible for different agents to use PCI while a single
			master retains ownership of LOCK#. The arbiter can
			implement a complete system lock. In this mode, if
			LOCK# is active, no other master can gain access to the
			system until the LOCK# is de-asserted.
			This signal is internally connected to a pull-up resistor.

DEVSEL#	E4	I/O	Device Select. DEVSEL# indicates that the driving	BHE#
			device has decoded its address as the target of the cur-
			rent access. As an input, DEVSEL# indicates whether
			any device on the bus has been selected. DEVSEL# is
			also driven by any agent that has the ability to accept
			cycles on a subtractive decode basis. As a master, if no
			DEVSEL# is detected within and up to the subtractive
			decode clock, a master abort cycle is initiated (except for
			special cycles which do not expect a DEVSEL#
			returned).
			This signal is internally connected to a pull-up resistor.

PERR#	H2	I/O	Parity Error. PERR# is used for reporting data parity	---
			errors during all PCI transactions except a Special Cycle.
			The PERR# line is driven two PCI clocks after the data in
			which the error was detected. This is one PCI clock after
			the PAR that is attached to the data. The minimum dura-
			tion of PERR# is one PCI clock for each data phase in
			which a data parity error is detected. PERR# must be
			driven high for one PCI clock before being placed in TRI-
			STATE. A target asserts PERR# on write cycles if it has
			claimed the cycle with DEVSEL#. The master asserts
			PERR# on read cycles.
			This signal is internally connected to a pull-up resistor.

SERR#	H1	I/O	System Error. SERR# can be asserted by any agent for	---
			reporting errors other than PCI parity. When the PFS bit
			is enabled in the GX1 module’s PCI Control Function 2
			register (Index 41h[5]), SERR# is asserted upon asser-
			tion of PERR#.
			This signal is internally connected to a pull-up resistor.

AMD Geode™ SC3200 Processor Data Book

55

Image 55

AMD SC3200 manual Lock#, Devsel#, Bhe#, Serr#

Contents

AMD Geode SC3200 Processor Data Book Publication ID 32581C Contacts Trademarks Advanced Micro Devices, Inc. All rights reserved Contents Video Processor Module Electrical SpecificationsPackage Specifications Core Logic Module ACCESS.bus Data Transaction Power Supply ConnectionsTypical Battery Configuration Typical Battery Current Normal Operation Mode 360 Multiword DMA Data Transfer Timing Diagram 388Fast IR MIR and FIR Timing Diagram 405 316 413 410411 412 32581C System Power States Serial Ports 1 and 2 Configuration RegisterACB1 and ACB2 Configuration Register Parallel Port Configuration Register 165 Banks 0 and 1 Common Control and Status Registers 116117 164 F3 PCI Header Registers for Audio Configuration Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F2BAR4+I/O Offset IDE Controller Configuration Registers Jtag Timing Parameters 418 QJC ×C/W 421 383385 387 SuperI/O General DescriptionVideo Processor Core Logic Video Processor Module FeaturesGeneral Features GX1 Processor Module Nand Eeprom Other FeaturesSuperI/O Module 32581C Memory Controller GX1 ModuleArchitecture Overview 32581C SC3200 Memory Controller Register Summary Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Registers MCMEMCNTRL2 R/W Rsvd Reserved. Write as GXBASE+840Ch-840Fh Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as 0070h Mcdradd R/W Mcgbaseadd R/WMcdracc R/W Video Input Port Fast-PCI BusDisplay 1 GX1 Module Interface System Reset Clock, Timers, and Reset LogicReset Logic Power-On Reset 32581C Memory ACCESS.busSystem Interface USB Ball Assignments Signal Definitions LegendMnemonic Definition AMD Geode BGU481 Ball Assignment Sorted by Ball Number Configuration RD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 32581CSignal Definitions BGU481 Ball Assignment Sorted Alphabetically by Signal NameSignal Name Ball No FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options TFT, PCI, GPIO, System Multiplexing ConfigurationTwo-Signal/Group Multiplexing Default Alternate Ball No Signal Configuration AC97 Fpci Monitoring Three-Signal/Group MultiplexingACCESS.bus Internal Test IDE2 Gpio PCI2TFT3 AB1 Gpio Four-Signal/Group Multiplexing Boot ROM is 16 Bits Wide. This strap signal enables Signal DescriptionsSignal Name Ball No Type Description Mux Maximum Core Clock Multiplier. These strap signals Column Address Strobe. RAS#, CAS#, WE# and CKE Memory Interface Signals Video Port Clock Input. The clock input from Video Port Interface Signals ACCESS.bus Interface Signals TFT Interface Signals Multiplexed Command and Byte Enables. During PCI Bus Interface SignalsMultiplexed Address and Data. a bus transaction con STOP# FRAME#IRDY# TRDY# SERR# LOCK#DEVSEL# BHE# USB REQ1#REQ0# VIP Sub-ISA Interface Signals IDE I/O Read Channels 0 and 1. IDEIOR0# is the read Low Pin Count LPC Bus Interface SignalsIDE Interface Signals IDE Chip Selects 0 and 1. These signals are used to Universal Serial Bus USB Interface Signals Data Terminal Ready Outputs. When low, indicate to Serial Ports UARTs Interface Signals Parallel Port Interface Signals IRRX1 AK8 Fast Infrared IR Port Interface SignalsSTB#/WRITE# FFRAME# Serial Bus Synchronization. This bit is asserted to syn 14 AC97 Audio Interface Signals KHz Output Clock Power Management Interface SignalsGeneral Purpose Wakeup I/Os. These signals each Suspend Power Plane Control 1 and 2. Control signal Gpio Interface Signals System Management Interrupt. This is the input to Debug Monitoring Interface SignalsJtag Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, this Thermal Diode Positive / Negative. These signals are Test and Measurement Interface SignalsPLL6, PLL5 and PLL2 Bypass. These signals are used Memory Internal Test Signals. These signals are used Power, Ground and No Connections1 Offset Width Bits Type Name Reset Value Reference Configuration Block AddressesGeneral Configuration Block Register Summary General Configuration Block 32581C Fpcimon Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies PMR27 Ball # IDE Signals Gpio and TFT Signals Name PP/ACB1/FPCI BitTFT Name Add’l Dependencies Rsvd Reserved. Write to Ball # Gpio Signals LPC Signals Name Add’l Dependencies Reserved 32581CGeneral Configuration Block Bit Description Offset 3Ch Interrupt Selection Register Intsel R/W Reset Value 00hReset Value xxh Offset 39h-3Bh Functional Description Watchdog Timer Usage Hints Watchdog RegistersWatchdog Interrupt 3describes the Watchdog registers Offset 05h-07h High-Resolution TimerHigh-Resolution Timer Registers Watchdog Status Register Wdsts R/WC Reset Value 00h Bit Description Offset 08h-0Bh Reset Value xxxxxxxxhTmclksel Timer Clock Select Tmen Timer Interrupt Enable Clock Generators and PLLs Clock Generation Block Diagram Crystal Oscillator Circuit Components 1 27 MHz Crystal OscillatorComponent Parameters Values Tolerance Strapped Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Core Clock Frequency Core Logic Module Clocks SuperI/O ClocksVideo Processor Clocks Clock Registers Clock Generator Configuration8describes the registers of the clock generator and PLL 1514 ISA Outstanding FeaturesAB1C AB1D AB2C AB2D System Wakeup Control SWC PC98 and Acpi CompliantSerial Port Serial Port 3 / Infrared IR Communication Port Internal Internal Signals AccessModule Architecture LDN Assignments Configuration Structure / AccessSIO Configuration Options Index-Data Register Pair Address Decoding Default Configuration Setup Standard Logical Device Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Logical Device Control and Configuration Registers Standard Configuration Registers 32581CSuperI/O Module Index F0h-FEh Logical Device Configuration R/WDMA Channel Select 1 R/W SID. SIO ID SIO Control and Configuration RegistersSIO Control and Configuration Register Map Index Type Name Power Rail Reset Value Relevant RTC Configuration Registers Logical Device Control and Configuration RTC Configuration Registers LDN 01h System Wakeup Control Relevant SWC RegistersBase Address MSB register Relevant IRCP/SP3 Registers 10. IRCP/SP3 Configuration Register LDN 03h and 08h Serial Ports 1 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register 11. Relevant Serial Ports 1 and 2 Registers 13. Relevant ACB1 and ACB2 Registers 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 ACB1 and ACB2 Configuration register 15. Relevant Parallel Port Registers 16. Parallel Port Configuration Register RTC Clock Generation X32I External X32O Battery = 0.1 μFReal-Time Clock RTC Bus Interface External Oscillator Signal ParametersExternal Elements Oscillator Startup Leap Years AlarmsTimekeeping Data Format Daylight Saving RTC Power SupplyBT1 18. System Power States Interrupt Handling Battery-Backed RAMs and Registers108 Index Type Name RTC Registers19. RTC Register Map 20. RTC Registers Index 04h Hours Register HOR R/W Index 05h Hours Alarm Register Hora R/W110 AMD Geode SC3200 Processor Data Book 111 Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO Index Programmable Century Register CEN R/W Rate Select Periodic Interrupt Divider Rate ms Chain Output 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding 23. BCD and Binary Formats 25. Extended RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM RTC General-Purpose RAM Map 24. Standard RAM Map Event Detection System Wakeup Control SWC26. Time Range Limits for Ceir Protocols Offset Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Wakeup Range 2 Registers Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Pulse Change, Range 1, High Limit AMD Geode SC3200 Processor Data Book 119 ACCESS.bus InterfaceData Transactions ABD ABC ABD MSB Acknowledge ACK CycleABC ACK Addressing Transfer Formats Master ModeAcknowledge After Every Byte Rule Arbitration on the Bus Master Stop Sending the Address ByteMaster Transmit Master Receive Configuration Slave Mode 31. ACB Register Map ACB Registers32. ACB Registers MASTER. RO Stop Stop Reserved Inten Interrupt EnableSaen Slave Address Enable EN Enable 34. Parallel Port Register Map for Second Level Offset Legacy Functional BlocksParallel Port 33. Parallel Port Register Map for First Level Offset 128 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset Bits Type Name Uart Functionality SP1 and SP2 41. Bank 3 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map 40. Bank 2 Register Map Register Bits Offset 42. Bank 0 Bit Map43. Bank 1 Bit Map Register Bits 45. Bank 3 Bit Map 44. Bank 2 Bit Map132 01h Register Throughout Offset 00h All Banks 3.1 IR/SP3 Mode Register Bank Overview46. Bank 0 Register Map IRCP/SP3 Register and Bit Maps BSR Bits Bank Selected Functionality 47. Bank Selection Encoding48. Bank 1 Register Map 49. Bank 2 Register Map 51. Bank 4 Register Map 50. Bank 3 Register Map52. Bank 5 Register Map 54. Bank 7 Register Map 53. Bank 6 Register Map55. Bank 0 Bit Map 59. Bank 4 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 58. Bank 3 Bit Map 61. Bank 6 Bit Map 60. Bank 5 Bit Map62. Bank 7 Bit Map Feature List Low Pin Count LPC Interface ConfigIntegrated Audio Video Processor Interface Pserial Interface Fast-PCI Interface to External PCI Bus Video Retrace Interrupt IDE Configuration RegistersPIO Mode IDE Controller Physical Region Descriptor Format DMARDY# Strobe Ideiordy UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode Stop Docw Universal Serial BusSub-ISA Bus Interface IOCS0#/IOCS1# Sub-ISA Bus Cycles Sub-ISA Support of Delayed PCI Transactions146 Sub-ISA Bus Data Steering 5.4 I/O Recovery DelaysREQ# GNT# FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# 148 ISA DMA PCI PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls ROM Interface DMA Channels FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA Controller DMA Priority DMA Transfer ModesDMA Controller Registers DMA Transfer Types DMA Address Generation Programmable Interval TimerDMA Addressing Capability DMA Page Registers and Extended Addressing Mapping PIC Interrupt MappingProgrammable Interrupt Controller Master PCI Compatible Interrupts PIC Interrupt SequencePIC I/O Registers PIC Shadow Register 7.2 I/O Port 061h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.1 I/O Port 092h System Control Power Management Logic Wakeup Events Capability Power Planes vs. Sleep/Global States Power Planes Control Signals vs Sleep StatesPower Management Events AMD Geode SC3200 Processor Data Book 159 Power ButtonPower Button Override Thermal Monitoring Suspend Modulation Power Management ProgrammingCPU Power Management APM Support Save-to-Disk Volt SuspendAMD Geode SC3200 Processor Data Book 161 Acpi Timer Register Peripheral Power ManagementDevice Idle Timers and Traps General Purpose Timers Module Power Management SMI Status Reporting RegistersF1BAR0+I/O F1BAR0+I/O Device Power Management Programming SummaryPower Management Programming Summary Located at F0 Index xxh Unless Otherwise Noted Integrated Audio Gpio Interface Size 11. Physical Region Descriptor FormatByte Audio Data Buffer PRD3 PRD1 PRD2 Codec Gpio Status and Control Registers Codec Configuration/Control RegistersCodec Command Register 12.2 AC97 Codec Interface Audio SMI Related Registers Trap SMI Enable RegisterVSA Technology Support Hardware VSA Technology Module Core Logic Module LPC Interface IRQ Configuration RegistersInternal IRQ Enable Register Internal IRQ Control Register 12. Cycle Types 13. PCI Configuration Address Register 0CF8h PCI Configuration Space and Access MethodsRegister Descriptions Register Summary Ter’s reset values and page references where the bit forMats are found Core Logic Module Register Summary 32581C Width Reset Reference F0 Index BitsAMD Geode SC3200 Processor Data Book 175 176 32581CCore Logic Module Register Summary F0BAR1+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR0+ F1BAR0+ 18. F1BAR0 SMI Status Registers Summary F1BAR1+ 19. F1BAR1 Acpi Support Registers SummaryAMD Geode SC3200 Processor Data Book 179 180 Width Reset Reference F2 Index Bits F2BAR4+ Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary 22. F3 PCI Header Registers for Audio Support Summary 182 Width Reset23. F3BAR0 Audio Support Registers Summary F3BAR0+ AMD Geode SC3200 Processor Data Book 183 Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary F5BAR0+ Width Reference Index Bits 26. Pciusb USB PCI Configuration Register SummaryName Reset Value Pciusb USBBAR0 27. Usbbar USB Controller Registers SummaryAMD Geode SC3200 Processor Data Book 185 DMA Page Registers Table 28. ISA Legacy I/O Register Summary186 Keyboard Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Programmable Interrupt Controller Registers Table Bridge, GPIO, and LPC Registers Function Chipset Register SpaceGeneral Remarks Data Parity Detected. This bit is set when Index 06h-07h PCI Status Register R/WAMD Geode SC3200 Processor Data Book 189 Index 0Ch Index 0Eh PCI Header Type RO Reset Value 80hBit Description Index 08h Index 09h-0Bh AMD Geode SC3200 Processor Data Book 191 PCI Subtractive Decode 192 Reset Control Register R/W Reset Value 01hIndex 42h Index 43h AMD Geode SC3200 Processor Data Book 193 Index 45hIndex 46h Index 47h PIT Counter 1 Enable Reset Value FFFFFFFFhReset Value 7Bh PIT Software Reset Generate SMI on A20M# Toggle ROM/AT Logic Control Register R/W Reset Value 98hAMD Geode SC3200 Processor Data Book 195 196 Bit Description Index 54h-59hIndex 5Ah Index 5Bh Decode Control Register 2 R/W INTC# Ball C9 Target Interrupt INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt INTD# Ball AA2 Target Interrupt 198 Index 76h Index 72hChip Select 1 Positive Decode IOCS1# Index 73h 200 Index 7Ch-7Fh DOCCS# Control Register R/W3127 DiskOnChip Chip Select Positive Decode DOCCS# AMD Geode SC3200 Processor Data Book 201 Index 81h Power Management Enable Register 2 R/W 202 AMD Geode SC3200 Processor Data Book 203 Power Management Enable Register 3 R/W Reset Value 00hKeyboard/Mouse Access Trap Parallel/Serial Access Trap 204 Floppy Disk Access TrapPrimary Hard Disk Access Trap Index 83h Power Management Enable Register 4 R/W AMD Geode SC3200 Processor Data Book 205 Index 84h Second Level PME/SMI Status Mirror Register 1 RO 206 AMD Geode SC3200 Processor Data Book 207 208 Index 88h General Purpose Timer 1 Count Register R/W AMD Geode SC3200 Processor Data Book 209 Re-trigger General Purpose Timer 1 on Floppy Disk Activity Index 8Dh Video Speedup Timer Count Register R/W Index 8Bh General Purpose Timer 2 Control Register R/W210 Index 93h Index 8Fh-92hAMD Geode SC3200 Processor Data Book 211 212 Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h Index 98h-99h Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/W Index B4h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B0h-B3h Index BAh PIT Shadow Register RO Index B9h PIC Shadow Register ROAMD Geode SC3200 Processor Data Book 215 Index C0h-C3h Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index BDh-BFh Index CEh Bit Description Index CChMask Index CDh 218 Index EDh-F3hIndex F4h Index F5h Second Level PME/SMI Status Register 2 RC AMD Geode SC3200 Processor Data Book 219 Index F6h Second Level PME/SMI Status Register 3 RC 220 Index F7h Second Level PME/SMI Status Register 4 RC Index F8h-FFh Ration registers are located. -29gives the bit formats 30. F0BAR0+I/O Offset Gpio Configuration RegistersI/O mapped registers accessed through F0BAR0 Gpio Support Registers F0BAR0+I/O Offset 18h is set, this edge generates a PME Offset 14h-17h GPDI1 Gpio Data In 1 Register ROAMD Geode SC3200 Processor Data Book 223 224 Bank AMD Geode SC3200 Processor Data Book 225 Reserved. Set to 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers 3121 AMD Geode SC3200 Processor Data Book 227 228 AMD Geode SC3200 Processor Data Book 229 Reserved Serial IRQ EnableSerial IRQ Interface Mode Number of IRQ Data Frames 230 LPC Midi Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Floppy Disk Controller Address Select. Selects I/O Port 232 Bit 32. F1 PCI Header Registers for SMI Status and Acpi Support SMI Status and Acpi Registers Function SMI Status Support Registers 33. F1BAR0+I/O Offset SMI Status RegistersAMD Geode SC3200 Processor Data Book 235 Offset 02h-03h Top Level PME/SMI Status Register RO/RC Suspend Modulation Enable Mirror. Read to Clear236 AMD Geode SC3200 Processor Data Book 237 238 Offset 04h-05h AMD Geode SC3200 Processor Data Book 239 These addresses should not be written Offset 1Ch-1Fh Offset 0Ah-1Bh240 3124 Offset 24h-27h External SMI Register R/WAMD Geode SC3200 Processor Data Book 241 242 AMD Geode SC3200 Processor Data Book 243 50h-FFh Offset 28h-4Fh Not Used Reset Value 00h244 Clkval Clock Throttling Value. CPU duty cycle Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Acpi Support Registers 246 1412 AMD Geode SC3200 Processor Data Book 247 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W 248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 Gpwio Control Register 2 R/W Reset Value 00h Reserved Gpwio Control Register 1 R/W Reset Value 00h252 AMD Geode SC3200 Processor Data Book 253 Gpwio Data Register R/W Reset Value 00hOffset 17h 3117 Reserved 254 Offset 21h-FFh IDE Controller Registers Function Bit Description Index 30h-3Fh PIOMODE. PIO mode256 AMD Geode SC3200 Processor Data Book 257 Reset Value 00009172hReset Value 00077771h 3024 258 Bit Description Index 50h-53hIndex 58h-5Bh Index 60h-FFh AMD Geode SC3200 Processor Data Book 259 IDE Controller Support Registers Offset 0Ch-0Fh Offset 09hOffset 0Ah Offset 0Bh Audio Registers Function 37. F3 PCI Header Registers for Audio Configuration Offset 04h-07h 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers 2921 AMD Geode SC3200 Processor Data Book 263 264 AMD Geode SC3200 Processor Data Book 265 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC 266 Reserved. Must be set to Mask Internal IRQ11. Write Only 32581CCore Logic Module Audio Registers FunctionMask Internal IRQ15. Write Only Mask Internal IRQ14. Write Only Reserved. Set to Assert Masked Internal IRQ12 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Assert Masked Internal IRQ14 270 Bit Description Assert Masked Internal IRQ1 Offset 2Ch-2Fh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ah-2Bh Offset 34h-37h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 32h-33h Offset 3Ch-3Fh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ah-3Bh Offset 44h-47h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 42h-43h Offset 4Ch-4Fh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ah-4Bh 39. F5 PCI Header Registers for X-Bus Expansion Bus Expansion Interface Function Index 24h-27h Core Logic Module X-Bus Expansion Interface Function 32581CBit Description Index 1Ch-1Fh Index 20h-23h Index 54h-57h F5BAR5 Mask Address Register R/W Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/W AMD Geode SC3200 Processor Data Book 279 Bit Description Index 64h-67h F5 Index 10h, Base Address Register 0 F5BAR0 set Base address that allows PCI access to additional I/O Con40. F5BAR0+I/O Offset X-Bus Expansion Registers Bus Expansion Support Registers Iostrapidselselect Idsel Strap Override Iotestporten Debug Test Port EnableAMD Geode SC3200 Processor Data Book 281 282 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb Bit Description Index 06h-07h Status Register R/W Reset Value 08hIndex 0Dh Latency Timer Register R/W Core Logic Module USB Controller Registers Pciusb 32581C Index 30h-3Bh Reset Value 0E11hReset Value A0F8h Reset Value 50h AMD Geode SC3200 Processor Data Book 285 42. USBBAR+Memory Offset USB Controller Registers FrameNumberOverflowEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable RootHubStatusChangeEnable 287 Offset 28h-2Bh Offset 38h-3Bh Reset Value = 00000628hReset Value = 01000003h Bit Description Offset 34h-37h AMD Geode SC3200 Processor Data Book 289 Read LocalPowerStatusChange. Not supported. Always readOffset 50h-53h HcRhStatus Register R/W 3018 290 AMD Geode SC3200 Processor Data Book HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus Read PortSuspendStatus AMD Geode SC3200 Processor Data Book 291 Bit Description Read PortEnableStatusRead CurrentConnectStatus 1510 292 319 Reserved. Read/Write 0s Reset Value = xxhOffset 60h-9Fh Offset 100h-103h 294 Reset Value = 000000xxhOffset 104h-107h 318 Reserved. Read/Write 0s 43. DMA Channel Control Registers ISA Legacy Register Space Write Priority ModeTiming Mode 32581CCore Logic Module ISA Legacy Register Space Address Direction Transfer ModeChannel Number Mode Select Bit Description Port 00Bh Undefined Write DMA Command Register, Channels298 Port 0D8h Bit Description Port 0D2hPort 0D4h Port 0D6h 44. DMA Page Registers 45. Programmable Interval Timer Registers Port 043h R/W Current Counter Mode BCD ModeBit Description Port 042h Write Counter Value Read 46. Programmable Interrupt Controller Registers IRQ1 / IRQ9 Mask Poll CommandRegister Read Mode Bit Description IRQ2 / IRQ10 Mask IRQ4 / IRQ12 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ5 / IRQ13 In-Service 47. Keyboard Controller Registers 49. Miscellaneous Registers 48. Real-Time Clock Registers 308 Graphics-Video Overlay and Blending General FeaturesVideo Input Port VIP Hardware Video Acceleration Mixer/Blender VIP AMD Geode SC3200 Processor Data Book 311 Functional DescriptionVideo Support VBI Support Active Video Video Input Port VIP Direct Video ModeGenLock Program other VIP bus master support registers Capture Video ModeBob Program the VIP bus master address registers AMD Geode SC3200 Processor Data Book 315 Weave Ping-pongs between the two buffers during runtime Field Interrupt Capture VBI Mode316 AMD Geode SC3200 Processor Data Book 317 Video BlockVideo Input Formatter Line Buffer Filtering Horizontal Downscaler with 4-Tap FilteringHorizontal Downscaler AMD Geode SC3200 Processor Data Book 319 Line BuffersFormatter 2.5 2-Tap Vertical and Horizontal Upscalers YUV Mixer/Blender BlockRGB RAM Color/Chroma Key Valid Mixing/Blending ConfigurationsYUV to RGB CSC in Video Data Path Gamma Correction Cursor Window Color/Chroma Key and Mixer/BlenderGraphics Window Video Window CHROMASEL1 Truth Table for Alpha BlendingMixing/Blending Operation Color 324 12. Color Key and Alpha Blending Logic T1 is a programmable multiple of frame time T0+T1 Power SequenceTFT Interface HSYNC, VSYNC, TFTDE, Tftdck 326 Integrated PLL F4 PCI Header Registers for Video Processor Support Summary F4BAR0 Video Processor Configuration Registers SummaryF4BAR0+ 328 32581CVideo Processor Module Register Summary F4BAR2+ F4BAR2 VIP Support Registers SummaryAMD Geode SC3200 Processor Data Book 329 3112 VIP Base Address 110 Address Range. Read Only Reset Value 0504hReset Value 030000h Video Processor Registers Function AMD Geode SC3200 Processor Data Book 331 Index 3Eh-FFh Reserved To 0 or 1 should be written with a value that is read Video Configuration Register R/W Reset Value 00000000hEN42X Enable 42x Format. Allows format selection Video Processor Support Registers F4BAR0 Reserved. Write as read Reserved Offset 04h-07h Display Configuration Register R/WAMD Geode SC3200 Processor Data Book 333 334 Bit Description Offset 08h-0Bh Video X Position Register R/W Offset 20h-23h Bit Description Offset 14h-17h Video Color Key Register R/W Clkdivsel Clock Divider Select Reset Value 00001400hReserved PLL2PWREN PLL2 Power-Down Enable Bit Description Offset 28h-2Bh FLTCO4 Filter Coefficient 4. For the tap-4 filter Reserved Signen Signature EnableDTS Downscale Type Select Offset 40h-43h Video Downscaler Coefficient Register R/W 338 Reserved Set to Offset 54h-57h Offset 50h-53hAMD Geode SC3200 Processor Data Book 339 340 Enable Alpha Window Disable Alpha Window 158 AMD Geode SC3200 Processor Data Book 341 342 ALPHA2VAL Value for Alpha Window Bit Description Offset 90h-93hOffset 94h-97h ALPHA3VAL Value for Alpha Window 3121 Reserved 200 Reserved. Set to Genlocktouten GenLock Timeout EnableCtgenlocken Enable Continuous GenLock Function Reserved. Set to Offset 424h-427h AMD Geode SC3200 Processor Data Book 345 F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 F4 Index 18h, Base Address Register 2 F4BAR2 points to 2322 Capture Store to Memory VBI DataCapture Store to Memory Video Data Reserved. Read Only Current Field. Read Only Start of each field Offset 14h-17h Bit Description Video Data Capture Active. Read OnlyRun Status. Read Only 3110 Reserved Offset 48h-4Bh VBI Data Pitch Register R/W Offset 44h-47h VBI Data Even Base Register R/W Optional Instruction Support Jtag Mode Instruction SupportTestability Jtag Mandatory Instruction Support 350 Absolute Maximum Ratings General SpecificationsPower/Ground Connections and Decoupling Electro Static Discharge ESD Operating Conditions Symbol Parameter Min Typ Max Unit CommentsVSS DC Current Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls Power State Parameter Definitions DC Characteristics for On State Symbol ParameterNote Min Typ Max Unit Comments DC Characteristics for Active Idle, Sleep, and Off StatesBall Capacitance and Inductance External PU or PD resistor Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors VIO 10. Buffer Types DC CharacteristicsSymbol Description Reference Wire Inbtn DC Characteristics Inab DC CharacteristicsInpci DC Characteristics INTS1 DC Characteristics Instrp DC CharacteristicsINT DC Characteristics Ints DC Characteristics ODn DC Characteristics Inusb DC Characteristics Ousb DC Characteristics Odpci DC CharacteristicsOp/n DC Characteristics Opci DC Characteristics CLK AC Characteristics11. Default Levels for Measurement Switching Parameters Symbol Parameter Value Outputs Memory Controller InterfaceInputs 364 32581CElectrical Specifications12. Memory Controller Timing Parameters SDCLK30, Sdclkout high time 233 MHz 266 MHz MD630 Data Valid Read Data T1, t2, t3SDCLK30 Control Output, MA120 BA10, MD630 Vpckin Vref Video Port 13. Video Input Port Timing Parameters Tftdck period time multiplexed on TFT Interface 14. TFT Timing ParametersTftdck rise/fall time between 0.8V Tftdck period time multiplexed on IDE 15. ACCESS.bus Input Timing Parameters ACCESS.bus Interface16. ACCESS.bus Output Timing Parameters AB1C AB2C AB1D AB2D AB1D AB2D AB1C AB1D AB2D AB1C AB2C370 PCI Bus Interface 17. PCI AC Specifications 64VIO 16VIOEquation a Equation B Pciclk 0.4 V IO 18. PCI Clock Parameters 19. PCI Timing Parameters 20. Measurement Condition Parameters Symbol Value Unit CommentsMeasurement and Test Conditions Ms typ PowerSignals Input Valid Bus Width Min Symbol Parameter Bits Type CommentsSub-ISA Interface 21. Sub-ISA Timing Parameters DOCR#/IOR# Bus Width Min Max Symbol Parameter Bits Type Comments IOW#/WR# MEMW#/DOCW# ROMCS#/DOCCS#IOR#/RD#/TRDE# MEMR#/DOCR# D150 DOCCS#/ROMCS#IOCS10# IOW#/WR# MEMW#/DOCW# TRDE# LPC Interface 22. LPC and Serirq Timing Parameters IDERST# pulse width IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDE Interface 23. IDE General Timing Parameters Width 8-bit min Mode Symbol Parameter Unit Comments24. IDE Register Transfer to/from Device Timing Parameters Cycle time min IDEIORDY0 2,3 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 Read IDEDATA70 AMD Geode SC3200 Processor Data Book 385 25. IDE PIO Data Transfer to/from Device Timing Parameters Read IDEDATA150 IDEIOR0# IDEIOW0# Write IDEDATA150386 26. IDE Multiword DMA Data Transfer Timing Parameters IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# IDECS10#388 27. IDE UltraDMA Data Burst Timing Parameters Mode Symbol Parameter Min Max Unit CommentsAMD Geode SC3200 Processor Data Book 389 IDEIRDY0 DSTROBE0 IDEREQ0STOP0 IDEIOR0# HDMARDY0# AMD Geode SC3200 Processor Data Book 391 IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host IDEDATA150 at host 392 IDEDREQ0 device IDEDACK0 hostIDEIOW0STOP0 host IDEIOR0HDMARDY0 IDEIOW0# STOP0# IDEDREQ0 deviceAMD Geode SC3200 Processor Data Book 393 IDEADDR20 IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDECS01# IDEIOR0# HSTROBE0# host DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIORDY0 DDMARDY0 device IDEDATA150 at device HSTROBE0#At host IDEDATA150 At host IDEIOR0# HSTROBE0# at device AMD Geode SC3200 Processor Data Book 397 IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# IDEIOR0# HSTROBE0# IDEDATA150 host IDEADDR20 IDECS01# IDEIORDY0# DDMARDY0# device398 IDEDATA150 host IDECS01# IDEADDR20 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostAMD Geode SC3200 Processor Data Book 399 Low Speed Source Note Full Speed Receiver EOP Width Note Low Speed Receiver EOP Width Note Source EOP widthHost upstream Receiver data jitter tolerance for paired Consecutive Transitions Rise Time Fall TimeDifferential Data Lines Differential Data Lines Crossover Points 2.0 Differential Crossover Points Data Lines Differential Data to SE0 SkewData Crossover Level EOP Width Setting of the Rxhsc bit bit 5 of the Rccfg register Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control SIR signal pulse width MIR Fast IR Port 30. Fast IR Port Timing ParametersFIR STB# Busy ACK# 32. Enhanced Parallel Port Timing Parameters Symbol Parameter MinUnit Comments Busy 33. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP AFD# BUSY# 34. ECP Reverse Mode Timing Parameters AC97RST# active low pulse width Audio Interface AC97 35. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay Sync inactive to Bitclk startup 162.8 Delay AC97CLK Vold 37. AC97 Clocks Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 38. AC97 I/O Timing Parameters 39. AC97 Signal Rise and Fall Timing Parameters Bitclk Sdataout 40. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low Slot ONCTL# PWRBTN# Power Management InterfacePower management event to ONCTL# Assertion 41. PWRBTN# Timing Parameters PWRBTN# ONTCL# PWRCNT21 POR# AMD Geode SC3200 Processor Data Book 417 POR# 32KHZ TDI, TMS hold time TDI, TMS setup timeNon-test inputs setup time Jtag Interface 45. Jtag Timing Parameters AMD Geode SC3200 Processor Data Book 419 Output SignalsInput Signals TDI TMS TDO 420 ΘJC ×C/W Thermal CharacteristicsCase-to-Ambient Thermal Resistance Example @ 85C Assume P max = 9W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 5W and TA max = 40C Therefore AMD Geode SC3200 Processor Data Book 423 Physical Dimensions 424 BGU481 Package Bottom View Degree C Package Order InformationOrdering Part Number Core Frequency MHz Table A-1. Revision History Data Book Revision HistoryRevision # Revisions / Comments Appendix a Data Book Revision History 32581C 89V toAMD Geode SC3200 Processor Data Book 427