AMD SC3200 manual PCI Clock Parameters, Pciclk 0.4 V IO

Electrical Specifications 32581C

Table 9-18. PCI Clock Parameters

Symbol	Parameter	Min	Max	Unit	Comments
tCYC	PCICLK cycle time	30		ns	Note 1
tHIGH	PCICLK high time	11		ns	Note 2
tLOW	PCICLK low time	11		ns	Note 2
PCICLKsr	PCICLK slew Rate	1	4	V/ns	Note 3
PCIRSTsr	PCIRST# slew Rate	50	-	mV/ns	Note 4

Note 1. Clock frequency is between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are not 100% tested. The clock can only be stopped in a low state.

Note 2. Guaranteed by characterization.

Note 3. Slew rate must be met across the minimum peak-to-peak portion of the clock waveform (see Figure 9-14).

Note 4. The minimum PCIRST# slew rate applies only to the rising (de-assertion) edge of the reset signal. See Figure 9-18for PCIRST# timing.

0.5 VIO			0.6VIO
					0.4 VIO, p-to-p
PCICLK 0.4 VIO						(minimum)
0.3 VIO
				0.2VIO
	t	HIGH		tLOW

tCYC

Figure 9-14. PCICLK Timing and Measurement Points

AMD Geode™ SC3200 Processor Data Book 373