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AMD SC3200 manual ISA Legacy I/O Register Summary, DMA Page Registers Table, 186

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32581CCore Logic Module - Register Summary

Table 6-28. ISA Legacy I/O Register Summary

I/O Port	Type	Name		Reference

DMA Channel Control Registers (Table 6-43)

000h	R/W	DMA Channel 0 Address Register		Page 295

001h	R/W	DMA Channel 0 Transfer Count Register		Page 295

002h	R/W	DMA Channel 1 Address Register		Page 295

003h	R/W	DMA Channel 1 Transfer Count Register		Page 295

004h	R/W	DMA Channel 2 Address Register		Page 295

005h	R/W	DMA Channel 2 Transfer Count Register		Page 295

006h	R/W	DMA Channel 3 Address Register		Page 295

007h	R/W	DMA Channel 3 Transfer Count Register		Page 295

008h	Read	DMA Status Register, Channels 3:0		Page 295

	Write	DMA Command Register, Channels 3:0		Page 296

009h	WO	Software DMA Request Register, Channels 3:0		Page 296

00Ah	W	DMA Channel Mask Register, Channels 3:0		Page 296

00Bh	WO	DMA Channel Mode Register, Channels 3:0		Page 297

00Ch	WO	DMA Clear Byte Pointer Command, Channels 3:0		Page 297

00Dh	WO	DMA Master Clear Command, Channels 3:0		Page 297

00Eh	WO	DMA Clear Mask Register Command, Channels 3:0		Page 297

00Fh	WO	DMA Write Mask Register Command, Channels 3:0		Page 297

0C0h	R/W	DMA Channel 4 Address Register (Not used)		Page 297

0C2h	R/W	DMA Channel 4 Transfer Count Register (Not Used)		Page 297

0C4h	R/W	DMA Channel 5 Address Register		Page 297

0C6h	R/W	DMA Channel 5 Transfer Count Register		Page 297

0C8h	R/W	DMA Channel 6 Address Register		Page 297

0CAh	R/W	DMA Channel 6 Transfer Count Register		Page 297

0CCh	R/W	DMA Channel 7 Address Register		Page 297

0CEh	R/W	DMA Channel 7 Transfer Count Register		Page 297

0D0h	Read	DMA Status Register, Channels 7:4		Page 298

	Write	DMA Command Register, Channels 7:4		Page 298

0D2h	WO	Software DMA Request Register, Channels 7:4		Page 299

0D4h	W	DMA Channel Mask Register, Channels 7:4		Page 299

0D6h	WO	DMA Channel Mode Register, Channels 7:4		Page 299

0D8h	WO	DMA Clear Byte Pointer Command, Channels 7:4		Page 299

0DAh	WO	DMA Master Clear Command, Channels 7:4		Page 299

0DCh	WO	DMA Clear Mask Register Command, Channels 7:4		Page 299

0DEh	WO	DMA Write Mask Register Command, Channels 7:4		Page 300

DMA Page Registers (Table 6-44)

081h	R/W	DMA Channel 2 Low Page Register		Page 300

082h	R/W	DMA Channel 3 Low Page Register		Page 300

083h	R/W	DMA Channel 1 Low Page Register		Page 300

087h	R/W	DMA Channel 0 Low Page Register		Page 300

089h	R/W	DMA Channel 6 Low Page Register		Page 300

08Ah	R/W	DMA Channel 7 Low Page Register		Page 300

08Bh	R/W	DMA Channel 5 Low Page Register		Page 300

08Fh	R/W	Sub-ISA Refresh Low Page Register		Page 300

481h	R/W	DMA Channel 2 High Page Register		Page 300

482h	R/W	DMA Channel 3 High Page Register		Page 300

483h	R/W	DMA Channel 1 High Page Register		Page 300


186			AMD Geode™ SC3200 Processor Data Book

Image 186

AMD SC3200 manual ISA Legacy I/O Register Summary, DMA Page Registers Table, 186

Contents

Publication ID 32581C AMD Geode SC3200 Processor Data BookAdvanced Micro Devices, Inc. All rights reserved Contacts TrademarksContents Core Logic Module Electrical SpecificationsPackage Specifications Video Processor ModuleTypical Battery Current Normal Operation Mode Power Supply ConnectionsTypical Battery Configuration ACCESS.bus Data Transaction316 Multiword DMA Data Transfer Timing Diagram 388Fast IR MIR and FIR Timing Diagram 405 360412 410411 41332581C Parallel Port Configuration Register Serial Ports 1 and 2 Configuration RegisterACB1 and ACB2 Configuration Register System Power States164 Banks 0 and 1 Common Control and Status Registers 116117 165F2BAR4+I/O Offset IDE Controller Configuration Registers Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F3 PCI Header Registers for Audio Configuration387 383385 Jtag Timing Parameters 418 QJC ×C/W 421Core Logic General DescriptionVideo Processor SuperI/OGX1 Processor Module FeaturesGeneral Features Video Processor ModuleOther Features Nand EepromSuperI/O Module 32581C GX1 Module Memory ControllerArchitecture Overview 32581C Width Memory Offset Bits Type Name/Function Reset Value SC3200 Memory Controller Register SummarySC3200 Memory Controller Registers MCMEMCNTRL2 R/W Rsvd Reserved. Write as 0070h Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as GXBASE+840Ch-840FhMcgbaseadd R/W Mcdradd R/WMcdracc R/W 1 GX1 Module Interface Fast-PCI BusDisplay Video Input PortPower-On Reset Clock, Timers, and Reset LogicReset Logic System Reset32581C Interface ACCESS.busSystem MemoryUSB Signal Definitions Legend Ball AssignmentsMnemonic Definition AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball NumberRD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 BGU481 Ball Assignment Sorted Alphabetically by Signal Name 32581CSignal DefinitionsSignal Name Ball No FSTOP# PD4 Vpckin Nominal External PU/PD Strap Settings Strap OptionsStrap Options Default Alternate Ball No Signal Configuration Multiplexing ConfigurationTwo-Signal/Group Multiplexing TFT, PCI, GPIO, SystemInternal Test Three-Signal/Group MultiplexingACCESS.bus AC97 Fpci MonitoringAB1 Gpio Gpio PCI2TFT3 IDE2Four-Signal/Group Multiplexing Maximum Core Clock Multiplier. These strap signals Signal DescriptionsSignal Name Ball No Type Description Mux Boot ROM is 16 Bits Wide. This strap signal enablesMemory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKEVideo Port Interface Signals Video Port Clock Input. The clock input fromTFT Interface Signals ACCESS.bus Interface SignalsPCI Bus Interface Signals Multiplexed Command and Byte Enables. DuringMultiplexed Address and Data. a bus transaction con TRDY# FRAME#IRDY# STOP#BHE# LOCK#DEVSEL# SERR#VIP REQ1#REQ0# USBSub-ISA Interface Signals IDE Chip Selects 0 and 1. These signals are used to Low Pin Count LPC Bus Interface SignalsIDE Interface Signals IDE I/O Read Channels 0 and 1. IDEIOR0# is the readUniversal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals Data Terminal Ready Outputs. When low, indicate toParallel Port Interface Signals FFRAME# Fast Infrared IR Port Interface SignalsSTB#/WRITE# IRRX1 AK814 AC97 Audio Interface Signals Serial Bus Synchronization. This bit is asserted to synSuspend Power Plane Control 1 and 2. Control signal Power Management Interface SignalsGeneral Purpose Wakeup I/Os. These signals each KHz Output ClockGpio Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, this Debug Monitoring Interface SignalsJtag Interface Signals System Management Interrupt. This is the input toMemory Internal Test Signals. These signals are used Test and Measurement Interface SignalsPLL6, PLL5 and PLL2 Bypass. These signals are used Thermal Diode Positive / Negative. These signals arePower, Ground and No Connections1 General Configuration Block 32581C Configuration Block AddressesGeneral Configuration Block Register Summary Offset Width Bits Type Name Reset Value ReferencePMR27 Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies FpcimonBall # IDE Signals Gpio and TFT Signals Name Bit PP/ACB1/FPCITFT Name Add’l Dependencies Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to32581CGeneral Configuration Block ReservedBit Description Offset 39h-3Bh Interrupt Selection Register Intsel R/W Reset Value 00hReset Value xxh Offset 3ChWatchdog Timer Functional Description3describes the Watchdog registers Watchdog RegistersWatchdog Interrupt Usage HintsWatchdog Status Register Wdsts R/WC Reset Value 00h High-Resolution TimerHigh-Resolution Timer Registers Offset 05h-07hTmen Timer Interrupt Enable Reset Value xxxxxxxxhTmclksel Timer Clock Select Bit Description Offset 08h-0BhClock Generation Block Diagram Clock Generators and PLLs1 27 MHz Crystal Oscillator Crystal Oscillator Circuit ComponentsComponent Parameters Values Tolerance Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Strapped Core Clock FrequencySuperI/O Clocks Core Logic Module ClocksVideo Processor Clocks Clock Generator Configuration Clock Registers8describes the registers of the clock generator and PLL 1514 Outstanding Features ISAAB1C AB1D AB2C AB2D Serial Port 3 / Infrared IR Communication Port PC98 and Acpi CompliantSerial Port System Wakeup Control SWCAccess Internal Internal SignalsModule Architecture Index-Data Register Pair Configuration Structure / AccessSIO Configuration Options LDN AssignmentsDefault Configuration Setup Address DecodingLogical Device Control and Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Standard Logical Device Configuration RegistersStandard Configuration Registers Index F0h-FEh Logical Device Configuration R/W 32581CSuperI/O ModuleDMA Channel Select 1 R/W Index Type Name Power Rail Reset Value SIO Control and Configuration RegistersSIO Control and Configuration Register Map SID. SIO IDLogical Device Control and Configuration Relevant RTC Configuration RegistersRTC Configuration Registers Relevant SWC Registers LDN 01h System Wakeup ControlBase Address MSB register 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers11. Relevant Serial Ports 1 and 2 Registers 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register LDN 03h and 08h Serial Ports 1ACB1 and ACB2 Configuration register 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 13. Relevant ACB1 and ACB2 Registers16. Parallel Port Configuration Register 15. Relevant Parallel Port RegistersBus Interface X32I External X32O Battery = 0.1 μFReal-Time Clock RTC RTC Clock GenerationOscillator Startup Signal ParametersExternal Elements External OscillatorDaylight Saving AlarmsTimekeeping Data Format Leap YearsPower Supply RTCBT1 18. System Power States Battery-Backed RAMs and Registers Interrupt Handling108 20. RTC Registers RTC Registers19. RTC Register Map Index Type NameIndex 05h Hours Alarm Register Hora R/W Index 04h Hours Register HOR R/W110 Index Programmable Century Register CEN R/W Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO AMD Geode SC3200 Processor Data Book 11123. BCD and Binary Formats 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding Rate Select Periodic Interrupt Divider Rate ms Chain OutputRTC General-Purpose RAM Map 24. Standard RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM 25. Extended RAM MapSystem Wakeup Control SWC Event Detection26. Time Range Limits for Ceir Protocols Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Offset Type Name Value29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Pulse Change, Range 1, High Limit Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Wakeup Range 2 RegistersABD ABC ACCESS.bus InterfaceData Transactions AMD Geode SC3200 Processor Data Book 119Acknowledge ACK Cycle ABD MSBABC ACK Arbitration on the Bus Master ModeAcknowledge After Every Byte Rule Addressing Transfer FormatsMaster Receive Sending the Address ByteMaster Transmit Master StopSlave Mode ConfigurationACB Registers 31. ACB Register Map32. ACB Registers MASTER. RO EN Enable Reserved Inten Interrupt EnableSaen Slave Address Enable Stop Stop33. Parallel Port Register Map for First Level Offset Legacy Functional BlocksParallel Port 34. Parallel Port Register Map for Second Level OffsetBits 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset 128Uart Functionality SP1 and SP2 Type Name40. Bank 2 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map 41. Bank 3 Register MapRegister Bits 42. Bank 0 Bit Map43. Bank 1 Bit Map Register Bits Offset44. Bank 2 Bit Map 45. Bank 3 Bit Map132 IRCP/SP3 Register and Bit Maps 3.1 IR/SP3 Mode Register Bank Overview46. Bank 0 Register Map 01h Register Throughout Offset 00h All Banks49. Bank 2 Register Map 47. Bank Selection Encoding48. Bank 1 Register Map BSR Bits Bank Selected Functionality50. Bank 3 Register Map 51. Bank 4 Register Map52. Bank 5 Register Map 53. Bank 6 Register Map 54. Bank 7 Register Map55. Bank 0 Bit Map 58. Bank 3 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 59. Bank 4 Bit Map60. Bank 5 Bit Map 61. Bank 6 Bit Map62. Bank 7 Bit Map Feature List Video Processor Interface ConfigIntegrated Audio Low Pin Count LPC InterfaceFast-PCI Interface to External PCI Bus Pserial InterfaceIDE Controller IDE Configuration RegistersPIO Mode Video Retrace InterruptPhysical Region Descriptor Format Stop UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode DMARDY# Strobe IdeiordyIOCS0#/IOCS1# Universal Serial BusSub-ISA Bus Interface DocwSub-ISA Support of Delayed PCI Transactions Sub-ISA Bus Cycles146 FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# 5.4 I/O Recovery DelaysREQ# GNT# Sub-ISA Bus Data SteeringISA DMA 148ROM Interface PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls PCIDMA Controller FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA ChannelsDMA Transfer Types DMA Transfer ModesDMA Controller Registers DMA PriorityDMA Page Registers and Extended Addressing Programmable Interval TimerDMA Addressing Capability DMA Address GenerationMaster PIC Interrupt MappingProgrammable Interrupt Controller MappingPIC Shadow Register PIC Interrupt SequencePIC I/O Registers PCI Compatible Interrupts7.1 I/O Port 092h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.2 I/O Port 061h System ControlPower Management Logic Wakeup Events Capability Power Planes Control Signals vs Sleep States Power Planes vs. Sleep/Global StatesPower Management Events Thermal Monitoring Power ButtonPower Button Override AMD Geode SC3200 Processor Data Book 159APM Support Power Management ProgrammingCPU Power Management Suspend ModulationVolt Suspend Save-to-DiskAMD Geode SC3200 Processor Data Book 161 General Purpose Timers Peripheral Power ManagementDevice Idle Timers and Traps Acpi Timer RegisterPower Management SMI Status Reporting Registers ModuleF1BAR0+I/O Located at F0 Index xxh Unless Otherwise Noted Device Power Management Programming SummaryPower Management Programming Summary F1BAR0+I/OGpio Interface Integrated AudioAudio Data Buffer 11. Physical Region Descriptor FormatByte SizePRD1 PRD2 PRD312.2 AC97 Codec Interface Codec Configuration/Control RegistersCodec Command Register Codec Gpio Status and Control RegistersVSA Technology Trap SMI Enable RegisterVSA Technology Support Hardware Audio SMI Related RegistersModule Core Logic Module Internal IRQ Control Register IRQ Configuration RegistersInternal IRQ Enable Register LPC Interface12. Cycle Types PCI Configuration Space and Access Methods 13. PCI Configuration Address Register 0CF8hRegister Descriptions Ter’s reset values and page references where the bit for Register SummaryMats are found Width Reset Reference F0 Index Bits Core Logic Module Register Summary 32581CAMD Geode SC3200 Processor Data Book 175 32581CCore Logic Module Register Summary 176F0BAR0+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR1+18. F1BAR0 SMI Status Registers Summary F1BAR0+19. F1BAR1 Acpi Support Registers Summary F1BAR1+AMD Geode SC3200 Processor Data Book 179 Width Reset Reference F2 Index Bits 18022. F3 PCI Header Registers for Audio Support Summary Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary F2BAR4+F3BAR0+ Width Reset23. F3BAR0 Audio Support Registers Summary 182F5BAR0+ Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary AMD Geode SC3200 Processor Data Book 183Pciusb 26. Pciusb USB PCI Configuration Register SummaryName Reset Value Width Reference Index Bits27. Usbbar USB Controller Registers Summary USBBAR0AMD Geode SC3200 Processor Data Book 185 28. ISA Legacy I/O Register Summary DMA Page Registers Table186 Programmable Interrupt Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Keyboard Controller Registers TableChipset Register Space Bridge, GPIO, and LPC Registers FunctionGeneral Remarks Index 06h-07h PCI Status Register R/W Data Parity Detected. This bit is set whenAMD Geode SC3200 Processor Data Book 189 Index 09h-0Bh Index 0Eh PCI Header Type RO Reset Value 80hBit Description Index 08h Index 0ChPCI Subtractive Decode AMD Geode SC3200 Processor Data Book 191Index 43h Reset Control Register R/W Reset Value 01hIndex 42h 192Index 47h Index 45hIndex 46h AMD Geode SC3200 Processor Data Book 193PIT Software Reset Reset Value FFFFFFFFhReset Value 7Bh PIT Counter 1 EnableROM/AT Logic Control Register R/W Reset Value 98h Generate SMI on A20M# ToggleAMD Geode SC3200 Processor Data Book 195 Index 5Bh Decode Control Register 2 R/W Bit Description Index 54h-59hIndex 5Ah 196INTD# Ball AA2 Target Interrupt INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt INTC# Ball C9 Target Interrupt198 Index 73h Index 72hChip Select 1 Positive Decode IOCS1# Index 76hDiskOnChip Chip Select Positive Decode DOCCS# Index 7Ch-7Fh DOCCS# Control Register R/W3127 200Index 81h Power Management Enable Register 2 R/W AMD Geode SC3200 Processor Data Book 201202 Parallel/Serial Access Trap Power Management Enable Register 3 R/W Reset Value 00hKeyboard/Mouse Access Trap AMD Geode SC3200 Processor Data Book 203Index 83h Power Management Enable Register 4 R/W Floppy Disk Access TrapPrimary Hard Disk Access Trap 204Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC3200 Processor Data Book 205206 AMD Geode SC3200 Processor Data Book 207 Index 88h General Purpose Timer 1 Count Register R/W 208Re-trigger General Purpose Timer 1 on Floppy Disk Activity AMD Geode SC3200 Processor Data Book 209Index 8Bh General Purpose Timer 2 Control Register R/W Index 8Dh Video Speedup Timer Count Register R/W210 Index 8Fh-92h Index 93hAMD Geode SC3200 Processor Data Book 211 Index 98h-99h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h 212Index A6h-A7h Video Idle Timer Count Register R/W Index A8h-A9h Video Overflow Count Register R/WIndex B0h-B3h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B4hIndex B9h PIC Shadow Register RO Index BAh PIT Shadow Register ROAMD Geode SC3200 Processor Data Book 215 Index BDh-BFh Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index C0h-C3hIndex CDh Bit Description Index CChMask Index CEhIndex F5h Second Level PME/SMI Status Register 2 RC Index EDh-F3hIndex F4h 218Index F6h Second Level PME/SMI Status Register 3 RC AMD Geode SC3200 Processor Data Book 219Index F7h Second Level PME/SMI Status Register 4 RC 220Index F8h-FFh Gpio Support Registers 30. F0BAR0+I/O Offset Gpio Configuration RegistersI/O mapped registers accessed through F0BAR0 Ration registers are located. -29gives the bit formatsOffset 14h-17h GPDI1 Gpio Data In 1 Register RO F0BAR0+I/O Offset 18h is set, this edge generates a PMEAMD Geode SC3200 Processor Data Book 223 Bank 224AMD Geode SC3200 Processor Data Book 225 3121 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers Reserved. Set toAMD Geode SC3200 Processor Data Book 227 228 Number of IRQ Data Frames Reserved Serial IRQ EnableSerial IRQ Interface Mode AMD Geode SC3200 Processor Data Book 229230 LPC Floppy Disk Controller Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port232 Bit SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support33. F1BAR0+I/O Offset SMI Status Registers SMI Status Support RegistersAMD Geode SC3200 Processor Data Book 235 Suspend Modulation Enable Mirror. Read to Clear Offset 02h-03h Top Level PME/SMI Status Register RO/RC236 AMD Geode SC3200 Processor Data Book 237 Offset 04h-05h 238AMD Geode SC3200 Processor Data Book 239 Offset 0Ah-1Bh These addresses should not be written Offset 1Ch-1Fh240 Offset 24h-27h External SMI Register R/W 3124AMD Geode SC3200 Processor Data Book 241 242 AMD Geode SC3200 Processor Data Book 243 Offset 28h-4Fh Not Used Reset Value 00h 50h-FFh244 Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Clkval Clock Throttling Value. CPU duty cycle1412 246Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 AMD Geode SC3200 Processor Data Book 247248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 Gpwio Control Register 1 R/W Reset Value 00h Gpwio Control Register 2 R/W Reset Value 00h Reserved252 3117 Reserved Gpwio Data Register R/W Reset Value 00hOffset 17h AMD Geode SC3200 Processor Data Book 253Offset 21h-FFh 254IDE Controller Registers Function PIOMODE. PIO mode Bit Description Index 30h-3Fh256 3024 Reset Value 00009172hReset Value 00077771h AMD Geode SC3200 Processor Data Book 257Index 60h-FFh Bit Description Index 50h-53hIndex 58h-5Bh 258IDE Controller Support Registers AMD Geode SC3200 Processor Data Book 259Offset 0Bh Offset 09hOffset 0Ah Offset 0Ch-0Fh37. F3 PCI Header Registers for Audio Configuration Audio Registers Function2921 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers Offset 04h-07hAMD Geode SC3200 Processor Data Book 263 264 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC AMD Geode SC3200 Processor Data Book 265266 Reserved. Must be set to Mask Internal IRQ14. Write Only 32581CCore Logic Module Audio Registers FunctionMask Internal IRQ15. Write Only Mask Internal IRQ11. Write OnlyAssert Masked Internal IRQ14 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Reserved. Set to Assert Masked Internal IRQ12Bit Description Assert Masked Internal IRQ1 270Offset 2Ah-2Bh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ch-2FhOffset 32h-33h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 34h-37hOffset 3Ah-3Bh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ch-3FhOffset 42h-43h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 44h-47hOffset 4Ah-4Bh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ch-4FhBus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus ExpansionIndex 20h-23h Core Logic Module X-Bus Expansion Interface Function 32581CBit Description Index 1Ch-1Fh Index 24h-27hIndex 50h-53h F5BAR4 Mask Address Register R/W Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 54h-57h F5BAR5 Mask Address Register R/WBit Description Index 64h-67h AMD Geode SC3200 Processor Data Book 279Bus Expansion Support Registers Base address that allows PCI access to additional I/O Con40. F5BAR0+I/O Offset X-Bus Expansion Registers F5 Index 10h, Base Address Register 0 F5BAR0 setIotestporten Debug Test Port Enable Iostrapidselselect Idsel Strap OverrideAMD Geode SC3200 Processor Data Book 281 Bit Description 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb 282Core Logic Module USB Controller Registers Pciusb 32581C Reset Value 08hIndex 0Dh Latency Timer Register R/W Index 06h-07h Status Register R/WReset Value 50h Reset Value 0E11hReset Value A0F8h Index 30h-3Bh42. USBBAR+Memory Offset USB Controller Registers AMD Geode SC3200 Processor Data Book 285RootHubStatusChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable FrameNumberOverflowEnableOffset 28h-2Bh 287Bit Description Offset 34h-37h Reset Value = 00000628hReset Value = 01000003h Offset 38h-3Bh3018 Read LocalPowerStatusChange. Not supported. Always readOffset 50h-53h HcRhStatus Register R/W AMD Geode SC3200 Processor Data Book 289Read PortSuspendStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus 290 AMD Geode SC3200 Processor Data Book1510 Bit Description Read PortEnableStatusRead CurrentConnectStatus AMD Geode SC3200 Processor Data Book 291292 Offset 100h-103h Reset Value = xxhOffset 60h-9Fh 319 Reserved. Read/Write 0s318 Reserved. Read/Write 0s Reset Value = 000000xxhOffset 104h-107h 294ISA Legacy Register Space 43. DMA Channel Control Registers32581CCore Logic Module ISA Legacy Register Space Priority ModeTiming Mode WriteBit Description Port 00Bh Transfer ModeChannel Number Mode Select Address DirectionWrite DMA Command Register, Channels Undefined298 Port 0D6h Bit Description Port 0D2hPort 0D4h Port 0D8h44. DMA Page Registers 45. Programmable Interval Timer Registers Counter Value Read Current Counter Mode BCD ModeBit Description Port 042h Write Port 043h R/W46. Programmable Interrupt Controller Registers Bit Description IRQ2 / IRQ10 Mask Poll CommandRegister Read Mode IRQ1 / IRQ9 MaskIRQ5 / IRQ13 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ4 / IRQ12 In-Service47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers308 Hardware Video Acceleration General FeaturesVideo Input Port VIP Graphics-Video Overlay and BlendingVIP Mixer/BlenderVBI Support Functional DescriptionVideo Support AMD Geode SC3200 Processor Data Book 311Active Video Direct Video Mode Video Input Port VIPGenLock Program the VIP bus master address registers Capture Video ModeBob Program other VIP bus master support registersWeave AMD Geode SC3200 Processor Data Book 315Field Interrupt Capture VBI Mode Ping-pongs between the two buffers during runtime316 Line Buffer Video BlockVideo Input Formatter AMD Geode SC3200 Processor Data Book 317Horizontal Downscaler with 4-Tap Filtering FilteringHorizontal Downscaler 2.5 2-Tap Vertical and Horizontal Upscalers Line BuffersFormatter AMD Geode SC3200 Processor Data Book 319RAM Mixer/Blender BlockRGB YUVGamma Correction Valid Mixing/Blending ConfigurationsYUV to RGB CSC in Video Data Path Color/Chroma KeyVideo Window Color/Chroma Key and Mixer/BlenderGraphics Window Cursor WindowColor Truth Table for Alpha BlendingMixing/Blending Operation CHROMASEL112. Color Key and Alpha Blending Logic 324HSYNC, VSYNC, TFTDE, Tftdck Power SequenceTFT Interface T1 is a programmable multiple of frame time T0+T1Integrated PLL 326F4BAR0 Video Processor Configuration Registers Summary F4 PCI Header Registers for Video Processor Support SummaryF4BAR0+ 32581CVideo Processor Module Register Summary 328F4BAR2 VIP Support Registers Summary F4BAR2+AMD Geode SC3200 Processor Data Book 329 Video Processor Registers Function Reset Value 0504hReset Value 030000h 3112 VIP Base Address 110 Address Range. Read OnlyIndex 3Eh-FFh Reserved AMD Geode SC3200 Processor Data Book 331Video Processor Support Registers F4BAR0 Video Configuration Register R/W Reset Value 00000000hEN42X Enable 42x Format. Allows format selection To 0 or 1 should be written with a value that is readOffset 04h-07h Display Configuration Register R/W Reserved. Write as read ReservedAMD Geode SC3200 Processor Data Book 333 Bit Description Offset 08h-0Bh Video X Position Register R/W 334Bit Description Offset 14h-17h Video Color Key Register R/W Offset 20h-23hBit Description Offset 28h-2Bh Reset Value 00001400hReserved PLL2PWREN PLL2 Power-Down Enable Clkdivsel Clock Divider SelectOffset 40h-43h Video Downscaler Coefficient Register R/W Reserved Signen Signature EnableDTS Downscale Type Select FLTCO4 Filter Coefficient 4. For the tap-4 filterReserved Set to 338Offset 50h-53h Offset 54h-57hAMD Geode SC3200 Processor Data Book 339 Enable Alpha Window Disable Alpha Window 158 340AMD Geode SC3200 Processor Data Book 341 342 ALPHA3VAL Value for Alpha Window Bit Description Offset 90h-93hOffset 94h-97h ALPHA2VAL Value for Alpha WindowReserved. Set to Offset 424h-427h Reserved. Set to Genlocktouten GenLock Timeout EnableCtgenlocken Enable Continuous GenLock Function 3121 Reserved 200F4 Index 18h, Base Address Register 2 F4BAR2 points to F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 AMD Geode SC3200 Processor Data Book 345Reserved. Read Only Current Field. Read Only Capture Store to Memory VBI DataCapture Store to Memory Video Data 23223110 Reserved Bit Description Video Data Capture Active. Read OnlyRun Status. Read Only Start of each field Offset 14h-17hOffset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/WMandatory Instruction Support Jtag Mode Instruction SupportTestability Jtag Optional Instruction Support350 Electro Static Discharge ESD General SpecificationsPower/Ground Connections and Decoupling Absolute Maximum RatingsSymbol Parameter Min Typ Max Unit Comments Operating ConditionsVSS Power State Parameter Definitions Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls DC CurrentDC Characteristics for On State DC Characteristics for Active Idle, Sleep, and Off States Symbol ParameterNote Min Typ Max Unit CommentsBall Capacitance and Inductance VIO Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors External PU or PD resistorWire DC CharacteristicsSymbol Description Reference 10. Buffer TypesInab DC Characteristics Inbtn DC CharacteristicsInpci DC Characteristics Ints DC Characteristics Instrp DC CharacteristicsINT DC Characteristics INTS1 DC CharacteristicsInusb DC Characteristics ODn DC CharacteristicsOpci DC Characteristics Odpci DC CharacteristicsOp/n DC Characteristics Ousb DC CharacteristicsSymbol Parameter Value AC Characteristics11. Default Levels for Measurement Switching Parameters CLKMemory Controller Interface OutputsInputs SDCLK30, Sdclkout high time 233 MHz 266 MHz 32581CElectrical Specifications12. Memory Controller Timing Parameters 364BA10, MD630 T1, t2, t3SDCLK30 Control Output, MA120 MD630 Data Valid Read DataVideo Port 13. Video Input Port Timing Parameters Vpckin VrefTftdck period time multiplexed on IDE TFT Interface 14. TFT Timing ParametersTftdck rise/fall time between 0.8V Tftdck period time multiplexed onACCESS.bus Interface 15. ACCESS.bus Input Timing Parameters16. ACCESS.bus Output Timing Parameters AB1D AB2D AB1C AB2CAB1D AB2D AB1C AB2C AB1D AB2D AB1C370 17. PCI AC Specifications PCI Bus Interface16VIO 64VIOEquation a Equation B 18. PCI Clock Parameters Pciclk 0.4 V IO19. PCI Timing Parameters Symbol Value Unit Comments 20. Measurement Condition ParametersMeasurement and Test Conditions Input Valid PowerSignals Ms typ21. Sub-ISA Timing Parameters Symbol Parameter Bits Type CommentsSub-ISA Interface Bus Width MinBus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR#MEMR#/DOCR# ROMCS#/DOCCS#IOR#/RD#/TRDE# IOW#/WR# MEMW#/DOCW#IOW#/WR# MEMW#/DOCW# TRDE# DOCCS#/ROMCS#IOCS10# D150LPC Interface 22. LPC and Serirq Timing Parameters IDE Interface 23. IDE General Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDERST# pulse widthCycle time min Mode Symbol Parameter Unit Comments24. IDE Register Transfer to/from Device Timing Parameters Width 8-bit minRead IDEDATA70 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 IDEIORDY0 2,325. IDE PIO Data Transfer to/from Device Timing Parameters AMD Geode SC3200 Processor Data Book 385IDEIOR0# IDEIOW0# Write IDEDATA150 Read IDEDATA150386 26. IDE Multiword DMA Data Transfer Timing Parameters IDECS10# IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0#388 Mode Symbol Parameter Min Max Unit Comments 27. IDE UltraDMA Data Burst Timing ParametersAMD Geode SC3200 Processor Data Book 389 IDEIOR0# HDMARDY0# IDEREQ0STOP0 IDEIRDY0 DSTROBE0IDEDATA150 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host AMD Geode SC3200 Processor Data Book 391IDEIOR0HDMARDY0 IDEDREQ0 device IDEDACK0 hostIDEIOW0STOP0 host 392IDEDREQ0 device IDEIOW0# STOP0#AMD Geode SC3200 Processor Data Book 393 IDECS01# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDEADDR20IDEIORDY0 DDMARDY0 device DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIOR0# HSTROBE0# hostIDEDATA150 At host IDEIOR0# HSTROBE0# at device HSTROBE0#At host IDEDATA150 at deviceIDEIOR0# HSTROBE0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# AMD Geode SC3200 Processor Data Book 397IDEIORDY0# DDMARDY0# device IDEDATA150 host IDEADDR20 IDECS01#398 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# host IDEDATA150 host IDECS01# IDEADDR20AMD Geode SC3200 Processor Data Book 399 Full Speed Receiver EOP Width Note Low Speed Source NoteReceiver data jitter tolerance for paired Source EOP widthHost upstream Low Speed Receiver EOP Width NoteDifferential Data Lines Crossover Points 2.0 Rise Time Fall TimeDifferential Data Lines Consecutive TransitionsEOP Width Differential Data to SE0 SkewData Crossover Level Differential Crossover Points Data LinesSIR signal pulse width Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control Setting of the Rxhsc bit bit 5 of the Rccfg registerFast IR Port 30. Fast IR Port Timing Parameters MIRFIR Busy ACK# STB#Symbol Parameter Min 32. Enhanced Parallel Port Timing ParametersUnit Comments AFD# 33. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP Busy34. ECP Reverse Mode Timing Parameters BUSY#Sync inactive to Bitclk startup 162.8 Delay Audio Interface AC97 35. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay AC97RST# active low pulse width37. AC97 Clocks Parameters AC97CLK Vold38. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN239. AC97 Signal Rise and Fall Timing Parameters Slot 40. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low Bitclk Sdataout41. PWRBTN# Timing Parameters Power Management InterfacePower management event to ONCTL# Assertion ONCTL# PWRBTN#PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC3200 Processor Data Book 417Jtag Interface 45. Jtag Timing Parameters TDI, TMS setup timeNon-test inputs setup time TDI, TMS hold timeTDI TMS TDO Output SignalsInput Signals AMD Geode SC3200 Processor Data Book 419420 Thermal Characteristics ΘJC ×C/WCase-to-Ambient Thermal Resistance Example @ 85C Assume P max = 5W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 9W and TA max = 40C ThereforePhysical Dimensions AMD Geode SC3200 Processor Data Book 423BGU481 Package Bottom View 424MHz Order InformationOrdering Part Number Core Frequency Degree C PackageData Book Revision History Table A-1. Revision HistoryRevision # Revisions / Comments 89V to Appendix a Data Book Revision History 32581CAMD Geode SC3200 Processor Data Book 427