AMD SC3200 manual IDE Register Transfer to/from Device Timing Parameters, Cycle time min

Electrical Specifications 32581C

Table 9-24. IDE Register Transfer to/from Device Timing Parameters

				Mode
Symbol	Parameter	0	1	2	3	5	Unit	Comments
t0	Cycle time (min)	600	383	240	180	120	ns	Note 1
t1	Address valid to IDE_IOR[0:1]#/	70	50	30	30	25	ns
	IDE_IOW[0:1]# setup (min)
t2	IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse	290	290	290	80	70	ns	Note 1
	width 8-bit (min)
t2i	IDE_IOR[0:1]#/IDE_IOW[0:1]#	-	-	-	70	25	ns	Note 1
	recovery time (min)
t3	IDE_IOW[0:1]# data setup (min)	60	45	30	30	20	ns
t4	IDE_IOW[0:1]# data hold (min)	30	20	15	10	10	ns
t5	IDE_IOR[0:1]# data setup (min)	50	35	20	20	20	ns
t6	IDE_IOR[0:1]# data hold (min)	5	5	5	5	5	ns
t6Z	IDE_IOR[0:1]# data TRI-STATE	30	30	30	30	30	ns	Note 2
	(max)
t9	IDE_IOR[0:1]#/IDE_IOW[0:1]# to	20	15	10	10	10	ns
	address valid hold (min)
tRD	Read data valid to IDE_IORDY[0:1]	0	0	0	0	0	ns
	active (if IDE_IORDY[0:1] initially low
	after tA (min)
tA	IDE_IORDY[0:1] setup time	35	35	35	35	35	ns	Note 3
tB	IDE_IORDY[0:1] pulse width (max)	1250	1250	1250	1250	1250	ns
tC	IDE_IORDY[0:1] assertion to release	5	5	5	5	5	ns
	(max)

Note 1. t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recov- ery time or command inactive time. The actual cycle time equals the sum of the command active time and the com- mand inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time requirements is greater than the sum of t2 and t2i. (This means that a host implementation can lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)

Note 2. This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven by the device (TRI-STATE).

Note 3. The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled. If IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the device is not driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t5 is met and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.

AMD Geode™ SC3200 Processor Data Book 383