AMD SC3200 manual Offset 60h-9Fh, Reset Value = xxh, Offset 100h-103h, Reserved. Read/Write 0s

Core Logic Module - USB Controller Registers - PCIUSB 32581C

	Table 6-42. USB_BAR+Memory Offset: USB Controller Registers (Continued)
Bit	Description

8Read: PortPowerStatus. This bit reflects the power state of the port regardless of the power switching mode.

0:Port power is off.

1:Port power is on.

If NoPowerSwitching is set, this bit is always read as 1.

Write: SetPortPower. Writing a 1 sets PortPowerStatus. Writing a 0 has no effect.

7:5 Reserved. Read/Write 0s.

4Read: PortResetStatus.

0:Port reset signal is not active.

1:Port reset signal is active.

Write: SetPortReset. Writing a 1 sets PortResetStatus. Writing a 0 has no effect.

3Read: PortOverCurrentIndicator. This bit reflects the state of the OVRCUR pin dedicated to this port. This field is only valid if NoOverCurrentProtection is cleared and OverCurrentProtectionMode is set.

0:No over-current condition.

1:Over-current condition.

Write: ClearPortSuspend. Writing a 1 initiates the selective resume sequence for the port. Writing a 0 has no effect.

2Read: PortSuspendStatus.

0:Port is not suspended.

1:Port is selectively suspended.

Write: SetPortSuspend. Writing a 1 sets PortSuspendStatus. Writing a 0 has no effect.

1Read: PortEnableStatus.

0:Port disabled.

1:Port enabled.

Write: SetPortEnable. Writing a 1 sets PortEnableStatus. Writing a 0 has no effect.

0Read: CurrentConnectStatus.

0:No device connected.

1:Device connected.

If DeviceRemoveable is set (not removable) this bit is always 1.

Write: ClearPortEnable. Writing 1 a clears PortEnableStatus. Writing a 0 has no effect.

Note: This register is reset by the UsbReset state.

Offset 60h-9Fh		Reserved	Reset Value = xxh
Offset 100h-103h		HceControl Register (R/W)	Reset Value = 00000000h
31:9	Reserved. Read/Write 0s.

8A20State. Indicates current state of Gate A20 on keyboard controller. Compared against value written to 60h when GateA20Sequence is active.

7IRQ12Active. Indicates a positive transition on IRQ12 from keyboard controller occurred. Software writes this bit to 1 to clear it (set it to 0); a 0 write has no effect.

6IRQ1Active. Indicates a positive transition on IRQ1 from keyboard controller occurred. Software writes this bit to 1 to clear it (set it to 0); a 0 write has no effect.

5GateA20Sequence. Set by HC when a data value of D1h is written to I/O port 64h. Cleared by HC on write to I/O port 64h of any value other than D1h.

4ExternalIRQEn. When set to 1, IRQ1 and IRQ12 from the keyboard controller cause an emulation interrupt. The function controlled by this bit is independent of the setting of the EmulationEnable bit in this register.

3IRQEn. When set, the HC generates IRQ1 or IRQ12 as long as the OutputFull bit in HceStatus is set to 1. If the AuxOut- putFull bit of HceStatus is 0, IRQ1 is generated: if 1, then an IRQ12 is generated.

2CharacterPending. When set, an emulation interrupt will be generated when the OutputFull bit of the HceStatus register is set to 0.

AMD Geode™ SC3200 Processor Data Book 293