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AMD SC3200 manual Bank 0 Bit Map, Bank 1 Bit Map, Register Bits Offset

Models: SC3200

1 428

Page 131

SuperI/O Module	32581C

Table 5-42. Bank 0 Bit Map

Register					Bits

Offset	Name	7	6	5	4	3	2	1	0

00h	RXD			RXD[7:0] (Receiver Data Bits)

	TXD			TXD[7:0] (Transmitter Data Bits)

01h	IER1		RSVD			MS_IE	LS_IE	TXLDL_IE	RXHDL_IE
	IER2	RSVD		TXEMP_IE	RSVD3/	MS_IE	LS_IE	TXLDL_IE	RXHDL_IE
					DMA_IE4
02h	EIR1	FEN[1:0]		RSVD		RXFT	IPR1	IPR0	IPF
	EIR2	RSVD		TXEMP_EV	RSVD 3/	MS_EV	LS_EV or	TXLDL_EV	RXHDL_EV
					DMA_EV 4		TXHLT_EV
	FCR	RXFTH[1:0]		TXFTH[1:0]		RSVD	TXSR	RXSR	FIFO_EN

03h	LCR5	BKSE	SBRK	STKP	EPS	PEN	STB	WLS[1:0]
	BSR5	BKSE			BSR[6:0] (Bank Select)
04h	MCR1		RSVD		LOOP	ISEN or	RILP	RTS	DTR
						DCDLP

	MCR2		RSVD			TX_DFR	RSVD	RTS	DTR
05h	LSR	ER_INF	TXEMP	TXRDY	BRK	FE	PE	OE	RXDA

06h	MSR	DCD	RI	DSR	CTS	DDCD	TERI	DDSR	DCTS

07h	SPR1				Scratch Data
	ASCR2	RSVD	TXUR4	RXACT4	RXWDG4	RSVD	S_OET4	RSVD	RXF_TOUT

1.Non-Extended Mode.

2.Extended Mode.

3.In SP1 only.

4.In SP2 only.

5.When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.

Table 5-43. Bank 1 Bit Map

Register

Bits

Offset

Name

00h

LBGD(L)

LBGD[7:0] (Low Byte)

01h

LBGD(H)

LBGD[15:8] (High Byte)

02h

RSVD

Reserved

03h

LCR1

BKSE

SBRK

STKP

EPS

PEN

STB

WLS[1:0]

BSR1

BKSE

BSR[6:0] (Bank Select)

04h-07h

RSVD

Reserved

1.When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.

AMD Geode™ SC3200 Processor Data Book

131

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Image 131

AMD manual Bank 0 Bit Map, Bank 1 Bit Map, Register Bits Offset, AMD Geode SC3200 Processor Data Book 131

Contents

AMD Geode SC3200 Processor Data Book Publication ID 32581CContacts Trademarks Advanced Micro Devices, Inc. All rights reservedContents Video Processor Module Electrical SpecificationsPackage Specifications Core Logic ModuleACCESS.bus Data Transaction Power Supply ConnectionsTypical Battery Configuration Typical Battery Current Normal Operation Mode360 Multiword DMA Data Transfer Timing Diagram 388Fast IR MIR and FIR Timing Diagram 405 316413 410411 41232581C System Power States Serial Ports 1 and 2 Configuration RegisterACB1 and ACB2 Configuration Register Parallel Port Configuration Register165 Banks 0 and 1 Common Control and Status Registers 116117 164F3 PCI Header Registers for Audio Configuration Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F2BAR4+I/O Offset IDE Controller Configuration RegistersJtag Timing Parameters 418 QJC ×C/W 421 383385 387SuperI/O General DescriptionVideo Processor Core LogicVideo Processor Module FeaturesGeneral Features GX1 Processor ModuleSuperI/O Module Other FeaturesNand Eeprom 32581C Architecture Overview 32581C GX1 ModuleMemory Controller SC3200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Register Summary MCMEMCNTRL2 R/W Rsvd Reserved. Write as GXBASE+840Ch-840Fh Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as 0070hMcdracc R/W Mcgbaseadd R/WMcdradd R/W Video Input Port Fast-PCI BusDisplay 1 GX1 Module InterfaceSystem Reset Clock, Timers, and Reset LogicReset Logic Power-On Reset32581C Memory ACCESS.busSystem InterfaceUSB Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode BGU481 Ball Assignment Sorted by Ball Number ConfigurationRD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 Signal Name Ball No BGU481 Ball Assignment Sorted Alphabetically by Signal Name32581CSignal Definitions FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options TFT, PCI, GPIO, System Multiplexing ConfigurationTwo-Signal/Group Multiplexing Default Alternate Ball No Signal ConfigurationAC97 Fpci Monitoring Three-Signal/Group MultiplexingACCESS.bus Internal TestIDE2 Gpio PCI2TFT3 AB1 GpioFour-Signal/Group Multiplexing Boot ROM is 16 Bits Wide. This strap signal enables Signal DescriptionsSignal Name Ball No Type Description Mux Maximum Core Clock Multiplier. These strap signalsColumn Address Strobe. RAS#, CAS#, WE# and CKE Memory Interface SignalsVideo Port Clock Input. The clock input from Video Port Interface SignalsACCESS.bus Interface Signals TFT Interface SignalsMultiplexed Address and Data. a bus transaction con PCI Bus Interface SignalsMultiplexed Command and Byte Enables. During STOP# FRAME#IRDY# TRDY#SERR# LOCK#DEVSEL# BHE#USB REQ1#REQ0# VIPSub-ISA Interface Signals IDE I/O Read Channels 0 and 1. IDEIOR0# is the read Low Pin Count LPC Bus Interface SignalsIDE Interface Signals IDE Chip Selects 0 and 1. These signals are used toUniversal Serial Bus USB Interface Signals Data Terminal Ready Outputs. When low, indicate to Serial Ports UARTs Interface SignalsParallel Port Interface Signals IRRX1 AK8 Fast Infrared IR Port Interface SignalsSTB#/WRITE# FFRAME#Serial Bus Synchronization. This bit is asserted to syn 14 AC97 Audio Interface SignalsKHz Output Clock Power Management Interface SignalsGeneral Purpose Wakeup I/Os. These signals each Suspend Power Plane Control 1 and 2. Control signalGpio Interface Signals System Management Interrupt. This is the input to Debug Monitoring Interface SignalsJtag Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, thisThermal Diode Positive / Negative. These signals are Test and Measurement Interface SignalsPLL6, PLL5 and PLL2 Bypass. These signals are used Memory Internal Test Signals. These signals are usedPower, Ground and No Connections1 Offset Width Bits Type Name Reset Value Reference Configuration Block AddressesGeneral Configuration Block Register Summary General Configuration Block 32581CFpcimon Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies PMR27Ball # IDE Signals Gpio and TFT Signals Name TFT Name Add’l Dependencies BitPP/ACB1/FPCI Rsvd Reserved. Write to Ball # Gpio Signals LPC Signals Name Add’l DependenciesReserved 32581CGeneral Configuration BlockBit Description Offset 3Ch Interrupt Selection Register Intsel R/W Reset Value 00hReset Value xxh Offset 39h-3BhFunctional Description Watchdog TimerUsage Hints Watchdog RegistersWatchdog Interrupt 3describes the Watchdog registersOffset 05h-07h High-Resolution TimerHigh-Resolution Timer Registers Watchdog Status Register Wdsts R/WC Reset Value 00hBit Description Offset 08h-0Bh Reset Value xxxxxxxxhTmclksel Timer Clock Select Tmen Timer Interrupt EnableClock Generators and PLLs Clock Generation Block DiagramComponent Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components Strapped Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Core Clock FrequencyVideo Processor Clocks SuperI/O ClocksCore Logic Module Clocks 8describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 1514 AB1C AB1D AB2C AB2D Outstanding FeaturesISA System Wakeup Control SWC PC98 and Acpi CompliantSerial Port Serial Port 3 / Infrared IR Communication PortModule Architecture AccessInternal Internal Signals LDN Assignments Configuration Structure / AccessSIO Configuration Options Index-Data Register PairAddress Decoding Default Configuration SetupStandard Logical Device Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Logical Device Control and Configuration RegistersStandard Configuration Registers DMA Channel Select 1 R/W Index F0h-FEh Logical Device Configuration R/W32581CSuperI/O Module SID. SIO ID SIO Control and Configuration RegistersSIO Control and Configuration Register Map Index Type Name Power Rail Reset ValueRelevant RTC Configuration Registers Logical Device Control and ConfigurationRTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control Relevant IRCP/SP3 Registers 10. IRCP/SP3 Configuration RegisterLDN 03h and 08h Serial Ports 1 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register 11. Relevant Serial Ports 1 and 2 Registers13. Relevant ACB1 and ACB2 Registers 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 ACB1 and ACB2 Configuration register15. Relevant Parallel Port Registers 16. Parallel Port Configuration RegisterRTC Clock Generation X32I External X32O Battery = 0.1 μFReal-Time Clock RTC Bus InterfaceExternal Oscillator Signal ParametersExternal Elements Oscillator StartupLeap Years AlarmsTimekeeping Data Format Daylight SavingBT1 Power SupplyRTC 18. System Power States 108 Battery-Backed RAMs and RegistersInterrupt Handling Index Type Name RTC Registers19. RTC Register Map 20. RTC Registers110 Index 05h Hours Alarm Register Hora R/WIndex 04h Hours Register HOR R/W AMD Geode SC3200 Processor Data Book 111 Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO Index Programmable Century Register CEN R/WRate Select Periodic Interrupt Divider Rate ms Chain Output 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding 23. BCD and Binary Formats25. Extended RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM RTC General-Purpose RAM Map 24. Standard RAM Map26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection Offset Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Type Name Value29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Wakeup Range 2 Registers Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Pulse Change, Range 1, High LimitAMD Geode SC3200 Processor Data Book 119 ACCESS.bus InterfaceData Transactions ABD ABCABC ACK Acknowledge ACK CycleABD MSB Addressing Transfer Formats Master ModeAcknowledge After Every Byte Rule Arbitration on the BusMaster Stop Sending the Address ByteMaster Transmit Master ReceiveConfiguration Slave Mode32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO Stop Stop Reserved Inten Interrupt EnableSaen Slave Address Enable EN Enable34. Parallel Port Register Map for Second Level Offset Legacy Functional BlocksParallel Port 33. Parallel Port Register Map for First Level Offset128 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset BitsType Name Uart Functionality SP1 and SP241. Bank 3 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map 40. Bank 2 Register MapRegister Bits Offset 42. Bank 0 Bit Map43. Bank 1 Bit Map Register Bits132 44. Bank 2 Bit Map45. Bank 3 Bit Map 01h Register Throughout Offset 00h All Banks 3.1 IR/SP3 Mode Register Bank Overview46. Bank 0 Register Map IRCP/SP3 Register and Bit MapsBSR Bits Bank Selected Functionality 47. Bank Selection Encoding48. Bank 1 Register Map 49. Bank 2 Register Map52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 59. Bank 4 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 58. Bank 3 Bit Map62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Low Pin Count LPC Interface ConfigIntegrated Audio Video Processor InterfacePserial Interface Fast-PCI Interface to External PCI BusVideo Retrace Interrupt IDE Configuration RegistersPIO Mode IDE ControllerPhysical Region Descriptor Format DMARDY# Strobe Ideiordy UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode StopDocw Universal Serial BusSub-ISA Bus Interface IOCS0#/IOCS1#146 Sub-ISA Support of Delayed PCI TransactionsSub-ISA Bus Cycles Sub-ISA Bus Data Steering 5.4 I/O Recovery DelaysREQ# GNT# FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR#148 ISA DMAPCI PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls ROM InterfaceDMA Channels FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA ControllerDMA Priority DMA Transfer ModesDMA Controller Registers DMA Transfer TypesDMA Address Generation Programmable Interval TimerDMA Addressing Capability DMA Page Registers and Extended AddressingMapping PIC Interrupt MappingProgrammable Interrupt Controller MasterPCI Compatible Interrupts PIC Interrupt SequencePIC I/O Registers PIC Shadow Register7.2 I/O Port 061h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.1 I/O Port 092h System ControlPower Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States AMD Geode SC3200 Processor Data Book 159 Power ButtonPower Button Override Thermal MonitoringSuspend Modulation Power Management ProgrammingCPU Power Management APM SupportAMD Geode SC3200 Processor Data Book 161 Volt SuspendSave-to-Disk Acpi Timer Register Peripheral Power ManagementDevice Idle Timers and Traps General Purpose TimersF1BAR0+I/O Power Management SMI Status Reporting RegistersModule F1BAR0+I/O Device Power Management Programming SummaryPower Management Programming Summary Located at F0 Index xxh Unless Otherwise NotedIntegrated Audio Gpio InterfaceSize 11. Physical Region Descriptor FormatByte Audio Data BufferPRD3 PRD1 PRD2Codec Gpio Status and Control Registers Codec Configuration/Control RegistersCodec Command Register 12.2 AC97 Codec InterfaceAudio SMI Related Registers Trap SMI Enable RegisterVSA Technology Support Hardware VSA TechnologyModule Core Logic Module LPC Interface IRQ Configuration RegistersInternal IRQ Enable Register Internal IRQ Control Register12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary AMD Geode SC3200 Processor Data Book 175 Width Reset Reference F0 Index BitsCore Logic Module Register Summary 32581C 176 32581CCore Logic Module Register SummaryF0BAR1+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR0+F1BAR0+ 18. F1BAR0 SMI Status Registers SummaryAMD Geode SC3200 Processor Data Book 179 19. F1BAR1 Acpi Support Registers SummaryF1BAR1+ 180 Width Reset Reference F2 Index BitsF2BAR4+ Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary 22. F3 PCI Header Registers for Audio Support Summary182 Width Reset23. F3BAR0 Audio Support Registers Summary F3BAR0+AMD Geode SC3200 Processor Data Book 183 Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary F5BAR0+Width Reference Index Bits 26. Pciusb USB PCI Configuration Register SummaryName Reset Value PciusbAMD Geode SC3200 Processor Data Book 185 27. Usbbar USB Controller Registers SummaryUSBBAR0 186 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Keyboard Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Programmable Interrupt Controller Registers TableGeneral Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function AMD Geode SC3200 Processor Data Book 189 Index 06h-07h PCI Status Register R/WData Parity Detected. This bit is set when Index 0Ch Index 0Eh PCI Header Type RO Reset Value 80hBit Description Index 08h Index 09h-0BhAMD Geode SC3200 Processor Data Book 191 PCI Subtractive Decode192 Reset Control Register R/W Reset Value 01hIndex 42h Index 43hAMD Geode SC3200 Processor Data Book 193 Index 45hIndex 46h Index 47hPIT Counter 1 Enable Reset Value FFFFFFFFhReset Value 7Bh PIT Software ResetAMD Geode SC3200 Processor Data Book 195 ROM/AT Logic Control Register R/W Reset Value 98hGenerate SMI on A20M# Toggle 196 Bit Description Index 54h-59hIndex 5Ah Index 5Bh Decode Control Register 2 R/WINTC# Ball C9 Target Interrupt INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt INTD# Ball AA2 Target Interrupt198 Index 76h Index 72hChip Select 1 Positive Decode IOCS1# Index 73h200 Index 7Ch-7Fh DOCCS# Control Register R/W3127 DiskOnChip Chip Select Positive Decode DOCCS#AMD Geode SC3200 Processor Data Book 201 Index 81h Power Management Enable Register 2 R/W202 AMD Geode SC3200 Processor Data Book 203 Power Management Enable Register 3 R/W Reset Value 00hKeyboard/Mouse Access Trap Parallel/Serial Access Trap204 Floppy Disk Access TrapPrimary Hard Disk Access Trap Index 83h Power Management Enable Register 4 R/WAMD Geode SC3200 Processor Data Book 205 Index 84h Second Level PME/SMI Status Mirror Register 1 RO206 AMD Geode SC3200 Processor Data Book 207 208 Index 88h General Purpose Timer 1 Count Register R/WAMD Geode SC3200 Processor Data Book 209 Re-trigger General Purpose Timer 1 on Floppy Disk Activity210 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W AMD Geode SC3200 Processor Data Book 211 Index 8Fh-92hIndex 93h 212 Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h Index 98h-99hIndex A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/WIndex B4h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B0h-B3hAMD Geode SC3200 Processor Data Book 215 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Index C0h-C3h Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index BDh-BFhIndex CEh Bit Description Index CChMask Index CDh218 Index EDh-F3hIndex F4h Index F5h Second Level PME/SMI Status Register 2 RCAMD Geode SC3200 Processor Data Book 219 Index F6h Second Level PME/SMI Status Register 3 RC220 Index F7h Second Level PME/SMI Status Register 4 RCIndex F8h-FFh Ration registers are located. -29gives the bit formats 30. F0BAR0+I/O Offset Gpio Configuration RegistersI/O mapped registers accessed through F0BAR0 Gpio Support RegistersAMD Geode SC3200 Processor Data Book 223 Offset 14h-17h GPDI1 Gpio Data In 1 Register ROF0BAR0+I/O Offset 18h is set, this edge generates a PME 224 BankAMD Geode SC3200 Processor Data Book 225 Reserved. Set to 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers 3121AMD Geode SC3200 Processor Data Book 227 228 AMD Geode SC3200 Processor Data Book 229 Reserved Serial IRQ EnableSerial IRQ Interface Mode Number of IRQ Data Frames230 LPC Midi Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Floppy Disk Controller Address Select. Selects I/O Port232 Bit 32. F1 PCI Header Registers for SMI Status and Acpi Support SMI Status and Acpi Registers FunctionAMD Geode SC3200 Processor Data Book 235 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers 236 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC AMD Geode SC3200 Processor Data Book 237 238 Offset 04h-05hAMD Geode SC3200 Processor Data Book 239 240 Offset 0Ah-1BhThese addresses should not be written Offset 1Ch-1Fh AMD Geode SC3200 Processor Data Book 241 Offset 24h-27h External SMI Register R/W3124 242 AMD Geode SC3200 Processor Data Book 243 244 Offset 28h-4Fh Not Used Reset Value 00h50h-FFh Clkval Clock Throttling Value. CPU duty cycle Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Acpi Support Registers246 1412AMD Geode SC3200 Processor Data Book 247 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 252 Gpwio Control Register 1 R/W Reset Value 00hGpwio Control Register 2 R/W Reset Value 00h Reserved AMD Geode SC3200 Processor Data Book 253 Gpwio Data Register R/W Reset Value 00hOffset 17h 3117 Reserved254 Offset 21h-FFhIDE Controller Registers Function 256 PIOMODE. PIO modeBit Description Index 30h-3Fh AMD Geode SC3200 Processor Data Book 257 Reset Value 00009172hReset Value 00077771h 3024258 Bit Description Index 50h-53hIndex 58h-5Bh Index 60h-FFhAMD Geode SC3200 Processor Data Book 259 IDE Controller Support RegistersOffset 0Ch-0Fh Offset 09hOffset 0Ah Offset 0BhAudio Registers Function 37. F3 PCI Header Registers for Audio ConfigurationOffset 04h-07h 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers 2921AMD Geode SC3200 Processor Data Book 263 264 AMD Geode SC3200 Processor Data Book 265 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC266 Reserved. Must be set to Mask Internal IRQ11. Write Only 32581CCore Logic Module Audio Registers FunctionMask Internal IRQ15. Write Only Mask Internal IRQ14. Write OnlyReserved. Set to Assert Masked Internal IRQ12 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Assert Masked Internal IRQ14270 Bit Description Assert Masked Internal IRQ1Offset 2Ch-2Fh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ah-2BhOffset 34h-37h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 32h-33hOffset 3Ch-3Fh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ah-3BhOffset 44h-47h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 42h-43hOffset 4Ch-4Fh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ah-4Bh39. F5 PCI Header Registers for X-Bus Expansion Bus Expansion Interface FunctionIndex 24h-27h Core Logic Module X-Bus Expansion Interface Function 32581CBit Description Index 1Ch-1Fh Index 20h-23hIndex 54h-57h F5BAR5 Mask Address Register R/W Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 50h-53h F5BAR4 Mask Address Register R/WAMD Geode SC3200 Processor Data Book 279 Bit Description Index 64h-67hF5 Index 10h, Base Address Register 0 F5BAR0 set Base address that allows PCI access to additional I/O Con40. F5BAR0+I/O Offset X-Bus Expansion Registers Bus Expansion Support RegistersAMD Geode SC3200 Processor Data Book 281 Iotestporten Debug Test Port EnableIostrapidselselect Idsel Strap Override 282 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb Bit DescriptionIndex 06h-07h Status Register R/W Reset Value 08hIndex 0Dh Latency Timer Register R/W Core Logic Module USB Controller Registers Pciusb 32581CIndex 30h-3Bh Reset Value 0E11hReset Value A0F8h Reset Value 50hAMD Geode SC3200 Processor Data Book 285 42. USBBAR+Memory Offset USB Controller RegistersFrameNumberOverflowEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable RootHubStatusChangeEnable287 Offset 28h-2BhOffset 38h-3Bh Reset Value = 00000628hReset Value = 01000003h Bit Description Offset 34h-37hAMD Geode SC3200 Processor Data Book 289 Read LocalPowerStatusChange. Not supported. Always readOffset 50h-53h HcRhStatus Register R/W 3018290 AMD Geode SC3200 Processor Data Book HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus Read PortSuspendStatusAMD Geode SC3200 Processor Data Book 291 Bit Description Read PortEnableStatusRead CurrentConnectStatus 1510292 319 Reserved. Read/Write 0s Reset Value = xxhOffset 60h-9Fh Offset 100h-103h294 Reset Value = 000000xxhOffset 104h-107h 318 Reserved. Read/Write 0s43. DMA Channel Control Registers ISA Legacy Register SpaceWrite Priority ModeTiming Mode 32581CCore Logic Module ISA Legacy Register SpaceAddress Direction Transfer ModeChannel Number Mode Select Bit Description Port 00Bh298 Write DMA Command Register, ChannelsUndefined Port 0D8h Bit Description Port 0D2hPort 0D4h Port 0D6h44. DMA Page Registers 45. Programmable Interval Timer Registers Port 043h R/W Current Counter Mode BCD ModeBit Description Port 042h Write Counter Value Read46. Programmable Interrupt Controller Registers IRQ1 / IRQ9 Mask Poll CommandRegister Read Mode Bit Description IRQ2 / IRQ10 MaskIRQ4 / IRQ12 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ5 / IRQ13 In-Service47. Keyboard Controller Registers 49. Miscellaneous Registers 48. Real-Time Clock Registers308 Graphics-Video Overlay and Blending General FeaturesVideo Input Port VIP Hardware Video AccelerationMixer/Blender VIPAMD Geode SC3200 Processor Data Book 311 Functional DescriptionVideo Support VBI SupportActive Video GenLock Direct Video ModeVideo Input Port VIP Program other VIP bus master support registers Capture Video ModeBob Program the VIP bus master address registersAMD Geode SC3200 Processor Data Book 315 Weave316 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime AMD Geode SC3200 Processor Data Book 317 Video BlockVideo Input Formatter Line BufferHorizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering AMD Geode SC3200 Processor Data Book 319 Line BuffersFormatter 2.5 2-Tap Vertical and Horizontal UpscalersYUV Mixer/Blender BlockRGB RAMColor/Chroma Key Valid Mixing/Blending ConfigurationsYUV to RGB CSC in Video Data Path Gamma CorrectionCursor Window Color/Chroma Key and Mixer/BlenderGraphics Window Video WindowCHROMASEL1 Truth Table for Alpha BlendingMixing/Blending Operation Color324 12. Color Key and Alpha Blending LogicT1 is a programmable multiple of frame time T0+T1 Power SequenceTFT Interface HSYNC, VSYNC, TFTDE, Tftdck326 Integrated PLLF4BAR0+ F4BAR0 Video Processor Configuration Registers SummaryF4 PCI Header Registers for Video Processor Support Summary 328 32581CVideo Processor Module Register SummaryAMD Geode SC3200 Processor Data Book 329 F4BAR2 VIP Support Registers SummaryF4BAR2+ 3112 VIP Base Address 110 Address Range. Read Only Reset Value 0504hReset Value 030000h Video Processor Registers FunctionAMD Geode SC3200 Processor Data Book 331 Index 3Eh-FFh ReservedTo 0 or 1 should be written with a value that is read Video Configuration Register R/W Reset Value 00000000hEN42X Enable 42x Format. Allows format selection Video Processor Support Registers F4BAR0AMD Geode SC3200 Processor Data Book 333 Offset 04h-07h Display Configuration Register R/WReserved. Write as read Reserved 334 Bit Description Offset 08h-0Bh Video X Position Register R/WOffset 20h-23h Bit Description Offset 14h-17h Video Color Key Register R/WClkdivsel Clock Divider Select Reset Value 00001400hReserved PLL2PWREN PLL2 Power-Down Enable Bit Description Offset 28h-2BhFLTCO4 Filter Coefficient 4. For the tap-4 filter Reserved Signen Signature EnableDTS Downscale Type Select Offset 40h-43h Video Downscaler Coefficient Register R/W338 Reserved Set toAMD Geode SC3200 Processor Data Book 339 Offset 50h-53hOffset 54h-57h 340 Enable Alpha Window Disable Alpha Window 158AMD Geode SC3200 Processor Data Book 341 342 ALPHA2VAL Value for Alpha Window Bit Description Offset 90h-93hOffset 94h-97h ALPHA3VAL Value for Alpha Window3121 Reserved 200 Reserved. Set to Genlocktouten GenLock Timeout EnableCtgenlocken Enable Continuous GenLock Function Reserved. Set to Offset 424h-427hAMD Geode SC3200 Processor Data Book 345 F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 F4 Index 18h, Base Address Register 2 F4BAR2 points to2322 Capture Store to Memory VBI DataCapture Store to Memory Video Data Reserved. Read Only Current Field. Read OnlyStart of each field Offset 14h-17h Bit Description Video Data Capture Active. Read OnlyRun Status. Read Only 3110 ReservedOffset 48h-4Bh VBI Data Pitch Register R/W Offset 44h-47h VBI Data Even Base Register R/WOptional Instruction Support Jtag Mode Instruction SupportTestability Jtag Mandatory Instruction Support350 Absolute Maximum Ratings General SpecificationsPower/Ground Connections and Decoupling Electro Static Discharge ESDVSS Symbol Parameter Min Typ Max Unit CommentsOperating Conditions DC Current Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls Power State Parameter DefinitionsDC Characteristics for On State Ball Capacitance and Inductance DC Characteristics for Active Idle, Sleep, and Off StatesSymbol ParameterNote Min Typ Max Unit Comments External PU or PD resistor Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors VIO10. Buffer Types DC CharacteristicsSymbol Description Reference WireInpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics INTS1 DC Characteristics Instrp DC CharacteristicsINT DC Characteristics Ints DC CharacteristicsODn DC Characteristics Inusb DC CharacteristicsOusb DC Characteristics Odpci DC CharacteristicsOp/n DC Characteristics Opci DC CharacteristicsCLK AC Characteristics11. Default Levels for Measurement Switching Parameters Symbol Parameter ValueInputs Memory Controller InterfaceOutputs 364 32581CElectrical Specifications12. Memory Controller Timing Parameters SDCLK30, Sdclkout high time 233 MHz 266 MHzMD630 Data Valid Read Data T1, t2, t3SDCLK30 Control Output, MA120 BA10, MD630Vpckin Vref Video Port 13. Video Input Port Timing ParametersTftdck period time multiplexed on TFT Interface 14. TFT Timing ParametersTftdck rise/fall time between 0.8V Tftdck period time multiplexed on IDE16. ACCESS.bus Output Timing Parameters ACCESS.bus Interface15. ACCESS.bus Input Timing Parameters AB1C AB2C AB1D AB2D370 AB1D AB2D AB1C AB2CAB1D AB2D AB1C PCI Bus Interface 17. PCI AC SpecificationsEquation a Equation B 16VIO64VIO Pciclk 0.4 V IO 18. PCI Clock Parameters19. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments20. Measurement Condition Parameters Ms typ PowerSignals Input ValidBus Width Min Symbol Parameter Bits Type CommentsSub-ISA Interface 21. Sub-ISA Timing ParametersDOCR#/IOR# Bus Width Min Max Symbol Parameter Bits Type CommentsIOW#/WR# MEMW#/DOCW# ROMCS#/DOCCS#IOR#/RD#/TRDE# MEMR#/DOCR#D150 DOCCS#/ROMCS#IOCS10# IOW#/WR# MEMW#/DOCW# TRDE#LPC Interface 22. LPC and Serirq Timing Parameters IDERST# pulse width IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDE Interface 23. IDE General Timing ParametersWidth 8-bit min Mode Symbol Parameter Unit Comments24. IDE Register Transfer to/from Device Timing Parameters Cycle time minIDEIORDY0 2,3 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 Read IDEDATA70AMD Geode SC3200 Processor Data Book 385 25. IDE PIO Data Transfer to/from Device Timing Parameters386 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 26. IDE Multiword DMA Data Transfer Timing Parameters 388 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC3200 Processor Data Book 389 Mode Symbol Parameter Min Max Unit Comments27. IDE UltraDMA Data Burst Timing Parameters IDEIRDY0 DSTROBE0 IDEREQ0STOP0 IDEIOR0# HDMARDY0#AMD Geode SC3200 Processor Data Book 391 IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host IDEDATA150 at host392 IDEDREQ0 device IDEDACK0 hostIDEIOW0STOP0 host IDEIOR0HDMARDY0AMD Geode SC3200 Processor Data Book 393 IDEDREQ0 deviceIDEIOW0# STOP0# IDEADDR20 IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDECS01#IDEIOR0# HSTROBE0# host DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIORDY0 DDMARDY0 deviceIDEDATA150 at device HSTROBE0#At host IDEDATA150 At host IDEIOR0# HSTROBE0# at deviceAMD Geode SC3200 Processor Data Book 397 IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# IDEIOR0# HSTROBE0#398 IDEIORDY0# DDMARDY0# deviceIDEDATA150 host IDEADDR20 IDECS01# AMD Geode SC3200 Processor Data Book 399 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Low Speed Source Note Full Speed Receiver EOP Width NoteLow Speed Receiver EOP Width Note Source EOP widthHost upstream Receiver data jitter tolerance for pairedConsecutive Transitions Rise Time Fall TimeDifferential Data Lines Differential Data Lines Crossover Points 2.0Differential Crossover Points Data Lines Differential Data to SE0 SkewData Crossover Level EOP WidthSetting of the Rxhsc bit bit 5 of the Rccfg register Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control SIR signal pulse widthFIR Fast IR Port 30. Fast IR Port Timing ParametersMIR STB# Busy ACK#Unit Comments Symbol Parameter Min32. Enhanced Parallel Port Timing Parameters Busy 33. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP AFD#BUSY# 34. ECP Reverse Mode Timing ParametersAC97RST# active low pulse width Audio Interface AC97 35. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay Sync inactive to Bitclk startup 162.8 DelayAC97CLK Vold 37. AC97 Clocks ParametersSDATAOUT/SYNC SDATAIN, SDATAIN2 38. AC97 I/O Timing Parameters39. AC97 Signal Rise and Fall Timing Parameters Bitclk Sdataout 40. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low SlotONCTL# PWRBTN# Power Management InterfacePower management event to ONCTL# Assertion 41. PWRBTN# Timing ParametersPWRBTN# ONTCL# PWRCNT21 POR# AMD Geode SC3200 Processor Data Book 417 POR# 32KHZTDI, TMS hold time TDI, TMS setup timeNon-test inputs setup time Jtag Interface 45. Jtag Timing ParametersAMD Geode SC3200 Processor Data Book 419 Output SignalsInput Signals TDI TMS TDO420 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Assume P max = 9W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 5W and TA max = 40C ThereforeAMD Geode SC3200 Processor Data Book 423 Physical Dimensions424 BGU481 Package Bottom ViewDegree C Package Order InformationOrdering Part Number Core Frequency MHzRevision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History AMD Geode SC3200 Processor Data Book 427 89V toAppendix a Data Book Revision History 32581C

32581C

Table 5-42. Bank 0 Bit Map

Register

Bits

ASCR2

RSVD

TXUR4

RXACT4

RXWDG4

S_OET4

RXF_TOUT

Table 5-43. Bank 1 Bit Map

Register

Bits

Offset

AMD Geode™ SC3200 Processor Data Book

131