AMD SC3200 manual Module Architecture, Access, Internal Internal Signals

SuperI/O Module 32581C

5.2Module Architecture

The SIO module comprises a collection of generic func- tional blocks. Each functional block is described in detail later in this chapter. The beginning of this chapter describes the SIO structure and provides all device specific information, including special implementation of generic blocks, system interface and device configuration.

The SIO module is based on eight logical devices, the host interface, and a central configuration register set, all built around a central, internal 8-bit bus.

The host interface serves as a bridge between the external ISA interface and the internal bus. It supports 8-bit I/O read, 8-bit I/O write and 8-bit DMA transactions, as defined in Personal Computer Bus Standard P996.

The central configuration register set supports ACPI com- pliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Reg- isters, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft®. All sys- tem resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines) are config- ured in, and managed by, the central configuration register set. In addition, some function-specific parameters are con- figurable through this unit and distributed to the functional blocks through special control signals.

The source of the device internal clocks is the 48 MHz clock signal or through the 32.768 KHz crystal with an internal frequency multiplier. RTC operates on a 32 KHz clock.

							IRTX/SOUT3		IRRX1/SIN3
ACK#							Infrared
AFD#/DSTRB#							Communication
BUSY/WAIT#										Serial
							Port/Serial Port 3
ERR#
			Parallel							Port 1
INIT#
PD[7:0]			Port
PE
SLCT
SLIN#/ASTRB#
STB#/WRITE#
										Serial
AB1C			ACCESS.				Configuration			Port 2
								and Control
AB1D			bus 1
								Registers
AB2C			ACCESS.
AB2D			bus 2							Internal
										Host
										Interface
Real-Time Clock (RTC)								System
								Wakeup
ALARM	X1C/X1	X2C	SB	BAT	Internal Bus	ControlSignals	RI2#	SDATAIN2	PWUREQ	CONFIG CLKIN MR D[7:0]	A[15:0]
			V	V
Internal										Internal Signals
Signal

Figure 5-2. Detailed SIO Block Diagram

SIN1

SOUT1

DTR#/BOUT1

SIN2

SOUT2

RTS2#

DTR2#/BOUT2

CTS2

RI2#

DCD2#

DSR2#

TC DACK0-3 DRQ0-3

IRQ1-12,14-15 Internal

IOCHRDY Signals ZWS#

IOWR#

IORD#

AEN

AMD Geode™ SC3200 Processor Data Book 89