AMD SC3200 manual Power Management Logic

32581C Core Logic Module

6.2.9Power Management Logic

The Core Logic module integrates advanced power man- agement features including idle timers for common system peripherals, address trap registers for programmable address ranges for I/O or memory accesses, four program- mable general purpose external inputs, clock throttling with automatic speedup for the GX1 clock, software GX1 stop clock, 0V Suspend/Resume with peripheral shadow regis- ters, and a dedicated serial bus to/from the GX1 module providing power management status.

The Core Logic module is ACPI (Advanced Configuration Power Interface) compliant. An ACPI-compliant system is one whose underlying BIOS, device drivers, chipset and peripherals conform to revision 1.0 of the ACPI specifica- tion. The Core Logic also supports Advanced Power Man- agement (APM).

The SC3200 provides the following support of ACPI states:

•CPU States: C0, C1, and C3.

•Sleep States:

—SL1/SL2 - ACPI S1 equivalent.

—SL3 - ACPI S3 equivalent.

—SL4 - ACPI S4 equivalent.

—SL5 - ACPI S5 equivalent.

•General Purpose Events: Fully programmable GPE0 Event Block registers.

•Wakeup Events: Supported through GPWIO[2:0] which are powered by standby voltage and generate SMIs. See registers at F1BAR1+I/O Offset 0Ah and F1BAR1+I/O Offset 12h. Also see Section 5.6 "System Wakeup Control (SWC)" on page 114 and Table 6-5 "Wakeup Events Capability" on page 157.

SC3200 device power management is highly tuned for low power systems. It allows the system designer to implement a wide range of power saving modes using a wide range of capabilities and configuration options.

SC3200 controls the following functions directly:

•The system clocks.

•Core processor power states.

•Wakeup/resume event detection, including general purpose events.

•Power supply and power planes.

It also supports systems with an external micro controller that is used as a power management controller.

6.2.9.1CPU States

The SC3200 supports three CPU states: C0, C1 and C3 (the Core Logic C2 CPU state is not supported). These states are fully compliant with the ACPI specification, revi- sion 1.0. These states occur in the Working state only (S0/ G0). They have no meaning when the system transitions into a Sleep state. For details on the various Sleep states, see Section 6.2.9.2 "Sleep States" on page 157.

C0 Power State - On

In this state the GX1 module executes code. This state has two sub-states: Full Speed or Throttling; selected via the THT_EN bit (F1BAR1+I/O Offset 00h[4]).

C1 Power State - Active Idle

The SC3200 enters the C1 state, when the Halt Instruction (HLT) is executed. It exits this state back to the C0 state upon an NMI, an unmasked interrupt, or an SMI. The Halt instruction stops program execution and generates a spe- cial Halt bus cycle. (See “Usage Hints” on page 159.)

Bus masters are supported in the C1 state and the SC3200 will temporarily exit C1 to perform a bus master transaction.

C2 Power State

The SC3200 does not support the C2 power state. All rele- vant registers and bit fields in the Core Logic are reserved.

C3 Power State

The SC3200 enters the C3 state, when the P_LVL3 register (F1BAR1+I/O Offset 05h) is read. It exits this state back to the C0 state (Full Speed or Throttling, depending on the THT_EN bit) upon:

•An NMI, an unmasked interrupt, or an SMI.

•A bus master request, if enabled via the BM_RLD bit (F1BAR1+I/O Offset 0Ch[1]).

In this state, the GX1 module is in Suspend Refresh mode (for details, see the Power Management section of the AMD Geode™ GX1 Processor Data Book, and Section 6.2.9.5 "Usage Hints" on page 159).

PCI arbitration should be disabled prior entering the C3 state via the ARB_DIS bit in the PM2_CNT register (F1BAR1+I/O Offset 20h[0]) because a PCI arbitration event could start after P_LVL3 has been read. After wakeup ARB_DIS needs to be cleared.

156 AMD Geode™ SC3200 Processor Data Book