AMD SC3200 manual Serial Ports 1 and 2 Configuration Register, Relevant ACB1 and ACB2 Registers

List of Tables 32581C

List of Tables

Table 2-1.	SC3200 Memory Controller Register Summary	. 18
Table 2-2.	SC3200 Memory Controller Registers	. 18
Table 3-1.	Signal Definitions Legend	. 27
Table 3-2.	BGU481 Ball Assignment - Sorted by Ball Number	. 29
Table 3-3.	BGU481 Ball Assignment - Sorted Alphabetically by Signal Name	. 40
Table 3-4.	Strap Options	. 44
Table 3-5.	Two-Signal/Group Multiplexing	. 45
Table 3-6.	Three-Signal/Group Multiplexing	. 46
Table 3-7.	Four-Signal/Group Multiplexing	. 48
Table 4-1.	General Configuration Block Register Summary	. 69
Table 4-2.	Multiplexing, Interrupt Selection, and Base Address Registers	. 70
Table 4-3.	WATCHDOG Registers	. 78
Table 4-4.	High-Resolution Timer Registers	. 80
Table 4-5.	Crystal Oscillator Circuit Components	. 82
Table 4-6.	Core Clock Frequency	. 83
Table 4-7.	Strapped Core Clock Frequency	. 83
Table 4-8.	Clock Generator Configuration	. 85
Table 5-1.	SIO Configuration Options	. 90
Table 5-2.	LDN Assignments	. 90
Table 5-3.	Standard Configuration Registers	. 93
Table 5-4.	SIO Control and Configuration Register Map	. 95
Table 5-5.	SIO Control and Configuration Registers	. 95
Table 5-6.	Relevant RTC Configuration Registers	. 96
Table 5-7.	RTC Configuration Registers	. 97
Table 5-8.	Relevant SWC Registers	. 98
Table 5-9.	Relevant IRCP/SP3 Registers	. 99
Table 5-10.	IRCP/SP3 Configuration Register	. 99
Table 5-11.	Relevant Serial Ports 1 and 2 Registers	100
Table 5-12.	Serial Ports 1 and 2 Configuration Register	100
Table 5-13.	Relevant ACB1 and ACB2 Registers	101
Table 5-14.	ACB1 and ACB2 Configuration Register	101
Table 5-15.	Relevant Parallel Port Registers	102
Table 5-16.	Parallel Port Configuration Register	102
Table 5-17.	Crystal Oscillator Circuit Components	103
Table 5-18.	System Power States	107
Table 5-19.	RTC Register Map	109
Table 5-20.	RTC Registers	109
Table 5-21.	Divider Chain Control / Test Selection	112
Table 5-22.	Periodic Interrupt Rate Encoding	112
Table 5-23.	BCD and Binary Formats	112
Table 5-24.	Standard RAM Map	113
Table 5-25.	Extended RAM Map	113
Table 5-26.	Time Range Limits for CEIR Protocols	114
Table 5-27.	Banks 0 and 1 - Common Control and Status Register Map	115
Table 5-28.	Bank 1 - CEIR Wakeup Configuration and Control Register Map	115
AMD Geode™ SC3200 Processor Data Book		9