AMD SC3200 manual PWR AD0 Inpci

Signal Definitions 32581C

Table 3-2. BGU481 Ball Assignment - Sorted by Ball Number (Continued)

Ball		I/O	Buffer1	Power
No.	Signal Name	(PU/PD)	Type	Rail	Configuration
R17	VSS	GND	---	---	---
R18	VSS	GND	---	---	---
R19	VSS	GND	---	---	---
R28	VSS	GND	---	---	---
R29	VSS	GND	---	---	---
R30	VSS	GND	---	---	---
R31	VSS	GND	---	---	---
T1	VCORE	PWR	---	---	---
T2	VCORE	PWR	---	---	---
T3	VCORE	PWR	---	---	---
T4	VCORE	PWR	---	---	---
T13	VSS	GND	---	---	---
T14	VSS	GND	---	---	---
T15	VSS	GND	---	---	---
T16	VSS	GND	---	---	---
T17	VSS	GND	---	---	---
T18	VSS	GND	---	---	---
T19	VSS	GND	---	---	---
T28	VCORE	PWR	---	---	---
T29	VCORE	PWR	---	---	---
T30	VCORE	PWR	---	---	---
T31	VCORE	PWR	---	---	---
U1	AD0	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	A0	O	OPCI
U2	IDE_ADDR2	O	O1/4	VIO	PMR[24] = 0
	TFTD4	O	O1/4		PMR[24] = 1
U3	AD2	I/O	INPCI,	VIO	Cycle Multiplexed
			OPCI
	A2	O	OPCI
U4	VCORE	PWR	---	---	---
U13	VSS	GND	---	---	---
U14	VSS	GND	---	---	---
U15	VSS	GND	---	---	---
U16	VSS	GND	---	---	---
U17	VSS	GND	---	---	---
U18	VSS	GND	---	---	---
U19	VSS	GND	---	---	---
U28	VCORE	PWR	---	---	---
U29	AC97_RST#	O	O2/5	VIO	FPCI_MON = 0
	F_STOP#	O	O2/5		FPCI_MON = 1
U30	BIT_CLK	I	INT	VIO	FPCI_MON = 0
	F_TRDY#	O	O1/4		FPCI_MON = 1

Ball		I/O	Buffer1	Power
No.	Signal Name	(PU/PD)	Type	Rail	Configuration
U31	SDATA_IN	I	INT	VIO	FPCI_MON = 0
	F_GNT0#	O	O2/5		FPCI_MON = 1
V1	IDE_DATA15	I/O	INTS1,	VIO	PMR[24] = 0
			TS1/4
	TFTD7	O	O1/4		PMR[24] = 1
V2	IDE_DATA14	I/O	INTS1,	VIO	PMR[24] = 0
			TS1/4
	TFTD17	O	O1/4		PMR[24] = 1
V3	IDE_DATA13	I/O	INTS1,	VIO	PMR[24] = 0
			TS1/4
	TFTD15	O	O1/4		PMR[24] = 1
V4	VSS	GND	---	---	---
V13	VCORE	PWR	---	---	---
V14	VCORE	PWR	---	---	---
V15	VSS	GND	---	---	---
V16	VSS	GND	---	---	---
V17	VSS	GND	---	---	---
V18	VCORE	PWR	---	---	---
V19	VCORE	PWR	---	---	---
V28	VSS	GND	---	---	---
V29	SDCLK3	O	O2/5	VIO	---
V30	GXCLK	O	O2/5	VIO	PMR[23]3 = 0 and
					PMR[29] = 0
	FP_VDD_ON	O	O1/4		PMR[23]3 = 1
	TEST3	O	O2/5		PMR[23]3 = 0 and
					PMR[29] = 1
V31	GPIO16	I/O	INT,	VIO	PMR[0] = 0 and
		(PU22.5)	O2/5		FPCI_MON = 0
	PC_BEEP	O	O2/5		PMR[0] = 1 = 0 and
					FPCI_MON = 0
	F_DEVSEL#	O	O2/5		FPCI_MON = 1
W1	VIO	PWR	---	---	---
W2	VSS	GND	---	---	---
W3	IDE_DATA12	I/O	INTS1,	VIO	PMR[24] = 0
			TS1/4
	TFTD13	O	O1/4		PMR[24] = 1
W4	IDE_DATA11	I/O	INTS1,	VIO	PMR[24] = 0
			TS1/4
	GPIO41	I/O	INTS1,		PMR[24] = 1
			O1/4
W13	VCORE	PWR	---	---	---
W14	VCORE	PWR	---	---	---
W15	VSS	GND	---	---	---
W16	VSS	GND	---	---	---
W17	VSS	GND	---	---	---
W18	VCORE	PWR	---	---	---
W19	VCORE	PWR	---	---	---

AMD Geode™ SC3200 Processor Data Book 35