32581C

Signal Definitions

3.4.1System Interface (Continued)

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

X32I

AJ2

I/O

Crystal Connections. Connected directly to a 32.768

---

 

 

 

KHz crystal. This clock input is required even if the inter-

 

X32O

AJ3

 

---

 

nal RTC is not being used. Some of the internal clocks

 

 

 

 

 

 

 

are derived from this clock. If an external clock is used, it

 

 

 

 

should be connected to X32I, using a voltage level of 0

 

 

 

 

volts to VCORE +10% maximum. X32O should remain

 

 

 

 

unconnected.

 

 

 

 

 

 

X27I

AG3

I/O

Crystal Connections. Connected directly to a

---

 

 

 

27.000 MHz crystal. Some of the internal clocks are

 

X27O

AH2

 

---

 

derived from this clock. If an external clock is used, it

 

 

 

 

 

 

 

should be connected to X27I, using a voltage level of 0

 

 

 

 

volts to VIO and X27O should be remain unconnected.

 

CLK27M

AA4

O

27 MHz Output Clock. Output of crystal oscillator.

IDE_DATA5

 

 

 

 

 

PCIRST#

A6

O

PCI and System Reset. PCIRST# is the reset signal for

---

 

 

 

the PCI bus and system. It is asserted for approximately

 

 

 

 

100 µs after POR# is negated.

 

 

 

 

 

 

3.4.2Memory Interface Signals

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

MD[63:0]

See

I/O

Memory Data Bus. The data bus lines driven to/from

---

 

Table 3-3

 

system memory.

 

 

on page

 

 

 

 

40.

 

 

 

 

 

 

 

 

MA[12:0]

See

O

Memory Address Bus. The multiplexed row/column

---

 

Table 3-3

 

address lines driven to the system memory. Supports

 

 

on page

 

256-Mbit SDRAM.

 

 

40.

 

 

 

 

 

 

 

 

BA1

AK14

O

Bank Address Bits. These bits are used to select the

---

 

 

 

component bank within the SDRAM.

 

BA0

AJ13

 

---

 

 

 

 

 

 

 

CS1#

AH27

O

Chip Selects. These bits are used to select the module

---

 

 

 

bank within system memory. Each chip select corre-

 

CS0#

AL12

 

---

 

sponds to a specific module bank. If CS# is high, the

 

 

 

 

 

 

 

bank(s) do not respond to RAS#, CAS#, and WE# until

 

 

 

 

the bank is selected again.

 

 

 

 

 

 

RASA#

AK12

O

Row Address Strobe. RAS#, CAS#, WE# and CKE are

---

 

 

 

encoded to support the different SDRAM commands.

 

 

 

 

RASA# is used with CS[1:0]#.

 

 

 

 

 

 

CASA#

AJ12

O

Column Address Strobe. RAS#, CAS#, WE# and CKE

---

 

 

 

are encoded to support the different SDRAM commands.

 

 

 

 

CASA# is used with CS[1:0]#.

 

 

 

 

 

 

WEA#

AH12

O

Write Enable. RAS#, CAS#, WE# and CKE are encoded

---

 

 

 

to support the different SDRAM commands. WEA# is

 

 

 

 

used with CS[1:0]#.

 

 

 

 

 

 

50

AMD Geode™ SC3200 Processor Data Book

Page 50
Image 50
AMD SC3200 manual Memory Interface Signals, Column Address Strobe. RAS#, CAS#, WE# and CKE