AMD SC3200 manual External Elements, Oscillator Startup, External Oscillator, Connections

32581C SuperI/O Module

External Elements

Choose C1 and C2 capacitors (see Figure 5-5 on page

103)to match the crystal’s load capacitance. The load

capacitance CL “seen” by crystal Y is comprised of C1 in series with C2 and in parallel with the parasitic capacitance of the circuit. The parasitic capacitance is caused by the chip package, board layout and socket (if any), and can vary from 0 to 10 pF. The rule of thumb in choosing these capacitors is:

CL = (C1 * C2) / (C1 + C2) + CPARASITIC

Example:

Crystal CL = 10 pF, CPARASITIC = 8.2 pF

C1 = 3.6 pF, C2 = 3.6 pF

Oscillator Startup

The oscillator starts to generate 32.768 KHz pulses to the RTC after about 100 ms from when VBAT is higher than

VBATMIN (2.4V) or VSB is higher than VSBMIN (3.0V). The oscillation amplitude on the X32O pin stabilizes to its final

value (approximately 0.4V peak-to-peak around 0.7V DC) in about 1 s.

C1 can be trimmed to achieve precisely 32.768 KHz. To achieve a high time accuracy, use crystal and capacitors with low tolerance and temperature coefficients.

5.5.2.2External Oscillator

32.768 KHz can be applied from an external clock source, as shown in Figure 5-6.

Connections

Connect the clock to the X32I ball, leaving the oscillator output, X32O, unconnected.

Signal Parameters

The signal levels should conform to the voltage level requirements for X32I, of square or sine wave of 0.0V to VCORE amplitude. The signal should have a duty cycle of approximately 50%. It should be sourced from a battery- backed source in order to oscillate during power-down. This assures that the RTC delivers updated time/calendar information.

5.5.2.3Timing Generation

The timing generation function divides the 32.768 KHz clock by 215 to derive a 1 Hz signal, which serves as the input for the seconds counter. This is performed by a divider chain composed of 15 divide-by-two latches, as shown in Figure 5-7.

Bits [6:4] (DV[2:0]) of the CRA Register control the follow- ing functions:

•Normal operation of the divider chain (counting).

•Divider chain reset to 0.

•Oscillator activity when only VBAT power is present (backup state).

The divider chain can be activated by setting normal opera- tional mode (bits [6:4] of CRA = 01x or 100). The first update occurs 500 ms after divider chain activation.

Bits [3:0] of CRA select one the of fifteen taps from the divider chain to be used as a periodic interrupt. The peri- odic flag becomes active after half of the programmed period has elapsed, following divider chain activation.

See Table 5-20 on page 109 for more details.

	VBAT			To other
				modules
	CF				Internal
					External
		CLKIN	X32O
		(X32I)	NC
		R2
		R1	3.3V square wave
		POWER	OUT	R1 = 30 KΩ
B1	CF		32.768 KHz
		Clock Generator		R	= 30 KΩ
Battery					2
				CF = 0.1 μF

Figure 5-6. External Oscillator Connections

		Divider Chain
1	2	3		13	14	15	1 Hz
2	2	2		2	2	2
				Reset
		DV2 DV1 DV0
		6	5	4
	CRA Register
32.768 KHz							Oscillator
			To other
							Enable
			modules
X32I	X32O

Figure 5-7. Divider Chain Control

104 AMD Geode™ SC3200 Processor Data Book