AMD SC3200 manual Integrated PLL, 326

32581C Video Processor Module

7.2.5Integrated PLL

The integrated PLL can generate frequencies up to 135 MHz from a single 27 MHz source. The clock frequency is programmable using two registers. Figure 7-14shows the block diagram of the Video Processor integrated PLL.

FREF is 27 MHz, generated by an external crystal and an integrated oscillator. FOUT is calculated from:

FOUT = (m + 1) / (n+ 1) x FREF

The integrated PLL can generate any frequency by writing into the “m” and “n” bit fields (FBAR0+Memory Offset 2Ch, m = bits [14:8] and n = bits [3:0]). Additionally, 16 prepro- grammed VGA frequencies can be selected via the PLL Clock Select register (F4BAR0+Memory Offset 2Ch[19:16]), if the crystal oscillator has a frequency of 27 MHz. This PLL can be powered down via the Miscella- neous register (F4BAR0+Memory Offset 28h[12]).

FREF

n

Divider

Phase	Charge	Loop	VCO
Compare	Pump	Filter
m
Divider

Out

Divide

FOUT

Figure 7-14. PLL Block Diagram

326 AMD Geode™ SC3200 Processor Data Book