AMD SC3200 manual Clock Generators and PLLs, Clock Generation Block Diagram

General Configuration Block 32581C

4.5Clock Generators and PLLs

This section describes the registers for the clocks required by the GX1 module, Core Logic module, and the Video Processor, and how these clocks are generated. See Fig- ure 4-2for a clock generation diagram.

The clock generators are based on 32.768 KHz and 27.000 MHz crystal oscillators. The 32.768 KHz crystal oscillator is described in Section 5.5.2 "RTC Clock Generation" on page 103 (functional description of the RTC).

32.768 KHz					Real-Time Clock (RTC)
32.768 KHz
Crystal		PLL4			USB Clock (48 MHz)
Oscillator					and I/O Block Clock
		48 MHz
Shutdown
					DISABLE
					AC97_CLK	To PAD
		PLL3			(24.576 MHz)
Shutdown	24.576 MHz
27 MHz					High-Resolution Timer Clock
Crystal
Oscillator				ACPI Clock (14.318 MHz)
		PLL6	Divide
Shutdown	57.273 MHz		by 4		CLK27M Ball
Shutdown					Dot Clock
Shutdown	CLK	PLL2
	25-135 MHz
DISABLE
			48 MHz
		PLL5			Internal Fast-PCI Clock
			66 MHz
	66.67 MHz
Shutdown
(ACPI)			33 MHz		External PCI Clock
		Divide			(33.3 MHz)
		by 2			DISABLE

ADL

100-333 MHz

Shutdown

(ACPI)

Divider

Core Clock

SDRAM Clock

Note: VPLL2 powers PLL2 and PLL5. VPLL3 powers PLL3, PLL4, and PLL6.

Figure 4-2. Clock Generation Block Diagram

AMD Geode™ SC3200 Processor Data Book 81