Reserved Serial IRQ Enable, Serial IRQ Interface Mode | AMD SC3200

Core Logic Module - Bridge, GPIO, and LPC Registers - Function 0

32581C

Table 6-31. F0BAR1+I/O Offset: LPC Interface Configuration Registers (Continued)

Bit		Description

2		SMI# Polarity. This bit allows signal polarity selection of the SMI# generated from LPC.
		0:	Active high.
		1:	Active low.

1		IRQ1 Polarity. If LPC is selected as the interface source for IRQ1 (F0BAR1+I/O Offset 00h[1] = 1), this bit allows signal
		polarity selection.
		0:	Active high.
		1:	Active low.

0		IRQ0 Polarity. If LPC is selected as the interface source for IRQ0 (F0BAR1+I/O Offset 00h[0] = 1), this bit allows signal
		polarity selection.
		0:	Active high.
		1:	Active low.

Offset 08h-0Bh				SERIRQ_CNT — Serial IRQ Control Register (R/W)		Reset Value: 00000000h

31:8		Reserved.

7		Serial IRQ Enable.
		0:	Disable.
		1:	Enable.

6		Serial IRQ Interface Mode.
		0:	Continuous.
		1:	Quiet.

5:2		Number of IRQ Data Frames.
		0000: 17 frames		0100: 21 frames	1000: 25 frames	1100: 29 frames
		0001: 18 frames		0101: 22 frames	1001: 26 frames	1101: 30 frames
		0010: 19 frames		0110: 23 frames	1010: 27 frames	1110: 31 frames
		0011: 20 frames		0111: 24 frames	1011: 28 frames	1111: 32 frames

1:0		Start Frame Pulse Width.
		00:	4 Clocks
		01:	6 Clocks
		10:	8 Clocks
		11: Reserved

Offset 0Ch-0Fh				DRQ_SRC — DRQ Source Register (R/W)		Reset Value: 00000000h
Note: DRQx are internal signals between the Core Logic and SuperI/O modules. Some signals require additional programming to
	make them externally accessible. See Table 4-2 "Multiplexing, Interrupt Selection, and Base Address Registers" on page 70 for
	pin multiplexing details and Table 3-4 "Strap Options" on page 44 for LPC_ROM strap information.

31:8		Reserved.

7		DRQ7 Source. Selects the interface source of the DRQ7 signal.
		0:	ISA - DRQ7 (unavailable externally).
		1: LPC - LDRQ# (ball L28).

6		DRQ6 Source. Selects the interface source of the DRQ6 signal.
		0:	ISA - DRQ6 (unavailable externally).
		1: LPC - LDRQ# (ball L28).

5		DRQ5 Source. Selects the interface source of the DRQ5 signal.
		0:	ISA - DRQ5 (unavailable externally).
		1: LPC - LDRQ# (ball L28).

4		LPC BM0 Cycles. Allow LPC Bus Master 0 Cycles.
		0:	Enable.
		1:	Disable.

3		DRQ3 Source. Selects the interface source of the DRQ3 signal.
		0:	ISA - DRQ3 (unavailable externally).
		1: LPC - LDRQ# (ball L28).


AMD Geode™ SC3200 Processor Data Book						229

Image 229

AMD SC3200 manual Reserved Serial IRQ Enable, Serial IRQ Interface Mode, Number of IRQ Data Frames

Contents

AMD Geode SC3200 Processor Data Book Publication ID 32581C Contacts Trademarks Advanced Micro Devices, Inc. All rights reserved Contents Package Specifications Electrical SpecificationsCore Logic Module Video Processor Module Typical Battery Configuration Power Supply ConnectionsTypical Battery Current Normal Operation Mode ACCESS.bus Data Transaction Fast IR MIR and FIR Timing Diagram 405 Multiword DMA Data Transfer Timing Diagram 388316 360 411 410412 413 32581C ACB1 and ACB2 Configuration Register Serial Ports 1 and 2 Configuration RegisterParallel Port Configuration Register System Power States 117 Banks 0 and 1 Common Control and Status Registers 116164 165 F0BAR0+I/O Offset Gpio Configuration Registers Pciusb USB PCI Configuration Register SummaryF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration 385 383387 Jtag Timing Parameters 418 QJC ×C/W 421 Video Processor General DescriptionCore Logic SuperI/O General Features FeaturesGX1 Processor Module Video Processor Module Nand Eeprom Other FeaturesSuperI/O Module 32581C Memory Controller GX1 ModuleArchitecture Overview 32581C SC3200 Memory Controller Register Summary Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Registers MCMEMCNTRL2 R/W Mcbankcfg R/W Bit Description GXBASE+8408h-840BhRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdradd R/W Mcgbaseadd R/WMcdracc R/W Display Fast-PCI Bus1 GX1 Module Interface Video Input Port Reset Logic Clock, Timers, and Reset LogicPower-On Reset System Reset 32581C System ACCESS.busInterface Memory USB Ball Assignments Signal Definitions LegendMnemonic Definition AMD Geode BGU481 Ball Assignment Sorted by Ball Number Configuration RD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 32581CSignal Definitions BGU481 Ball Assignment Sorted Alphabetically by Signal NameSignal Name Ball No FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options Two-Signal/Group Multiplexing Multiplexing ConfigurationDefault Alternate Ball No Signal Configuration TFT, PCI, GPIO, System ACCESS.bus Three-Signal/Group MultiplexingInternal Test AC97 Fpci Monitoring TFT3 Gpio PCI2AB1 Gpio IDE2 Four-Signal/Group Multiplexing Signal Name Ball No Type Description Mux Signal DescriptionsMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enables Column Address Strobe. RAS#, CAS#, WE# and CKE Memory Interface Signals Video Port Clock Input. The clock input from Video Port Interface Signals ACCESS.bus Interface Signals TFT Interface Signals Multiplexed Command and Byte Enables. During PCI Bus Interface SignalsMultiplexed Address and Data. a bus transaction con IRDY# FRAME#TRDY# STOP# DEVSEL# LOCK#BHE# SERR# REQ0# REQ1#VIP USB Sub-ISA Interface Signals IDE Interface Signals Low Pin Count LPC Bus Interface SignalsIDE Chip Selects 0 and 1. These signals are used to IDE I/O Read Channels 0 and 1. IDEIOR0# is the read Universal Serial Bus USB Interface Signals Data Terminal Ready Outputs. When low, indicate to Serial Ports UARTs Interface Signals Parallel Port Interface Signals STB#/WRITE# Fast Infrared IR Port Interface SignalsFFRAME# IRRX1 AK8 Serial Bus Synchronization. This bit is asserted to syn 14 AC97 Audio Interface Signals General Purpose Wakeup I/Os. These signals each Power Management Interface SignalsSuspend Power Plane Control 1 and 2. Control signal KHz Output Clock Gpio Interface Signals Jtag Interface Signals Debug Monitoring Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input to PLL6, PLL5 and PLL2 Bypass. These signals are used Test and Measurement Interface SignalsMemory Internal Test Signals. These signals are used Thermal Diode Positive / Negative. These signals are Power, Ground and No Connections1 General Configuration Block Register Summary Configuration Block AddressesGeneral Configuration Block 32581C Offset Width Bits Type Name Reset Value Reference Other Signal Add’l Dependencies Ball # Internal Test Signals Name Add’l DependenciesPMR27 Fpcimon Ball # IDE Signals Gpio and TFT Signals Name PP/ACB1/FPCI BitTFT Name Add’l Dependencies Rsvd Reserved. Write to Ball # Gpio Signals LPC Signals Name Add’l Dependencies Reserved 32581CGeneral Configuration Block Bit Description Reset Value xxh Interrupt Selection Register Intsel R/W Reset Value 00hOffset 39h-3Bh Offset 3Ch Functional Description Watchdog Timer Watchdog Interrupt Watchdog Registers3describes the Watchdog registers Usage Hints High-Resolution Timer Registers High-Resolution TimerWatchdog Status Register Wdsts R/WC Reset Value 00h Offset 05h-07h Tmclksel Timer Clock Select Reset Value xxxxxxxxhTmen Timer Interrupt Enable Bit Description Offset 08h-0Bh Clock Generators and PLLs Clock Generation Block Diagram Crystal Oscillator Circuit Components 1 27 MHz Crystal OscillatorComponent Parameters Values Tolerance Internal Fast-PCI Clock 2 GX1 Module Core ClockCore Clock Frequency Strapped Core Clock Frequency Core Logic Module Clocks SuperI/O ClocksVideo Processor Clocks Clock Registers Clock Generator Configuration8describes the registers of the clock generator and PLL 1514 ISA Outstanding FeaturesAB1C AB1D AB2C AB2D Serial Port PC98 and Acpi CompliantSerial Port 3 / Infrared IR Communication Port System Wakeup Control SWC Internal Internal Signals AccessModule Architecture SIO Configuration Options Configuration Structure / AccessIndex-Data Register Pair LDN Assignments Address Decoding Default Configuration Setup SIO Control and Configuration Registers Standard Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers 32581CSuperI/O Module Index F0h-FEh Logical Device Configuration R/WDMA Channel Select 1 R/W SIO Control and Configuration Register Map SIO Control and Configuration RegistersIndex Type Name Power Rail Reset Value SID. SIO ID Relevant RTC Configuration Registers Logical Device Control and Configuration RTC Configuration Registers LDN 01h System Wakeup Control Relevant SWC RegistersBase Address MSB register Relevant IRCP/SP3 Registers 10. IRCP/SP3 Configuration Register Serial Ports 1 and 2 Configuration register 12. Serial Ports 1 and 2 Configuration Register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 1 LDN 05h and 06h ACCESS.bus Ports 1 14. ACB1 and ACB2 Configuration RegisterACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers 15. Relevant Parallel Port Registers 16. Parallel Port Configuration Register Real-Time Clock RTC X32I External X32O Battery = 0.1 μFBus Interface RTC Clock Generation External Elements Signal ParametersOscillator Startup External Oscillator Timekeeping Data Format AlarmsDaylight Saving Leap Years RTC Power SupplyBT1 18. System Power States Interrupt Handling Battery-Backed RAMs and Registers108 19. RTC Register Map RTC Registers20. RTC Registers Index Type Name Index 04h Hours Register HOR R/W Index 05h Hours Alarm Register Hora R/W110 Index 0Ch RTC Control Register C CRC RO Index Programmable Month Alarm Register Mona R/WIndex Programmable Century Register CEN R/W AMD Geode SC3200 Processor Data Book 111 22. Periodic Interrupt Rate Encoding 21. Divider Chain Control / Test Selection23. BCD and Binary Formats Rate Select Periodic Interrupt Divider Rate ms Chain Output 00h 7Fh Battery-backed general-purpose Byte RAM 0Eh 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM Map Event Detection System Wakeup Control SWC26. Time Range Limits for Ceir Protocols 27. Banks 0 and 1 Common Control and Status Register Map SWC RegistersType Name Value Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bank 1, Offset 0Ah IRWTR1L Register R/W Bit Description Ceir Wakeup Range 1 RegistersCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 Registers Data Transactions ACCESS.bus InterfaceABD ABC AMD Geode SC3200 Processor Data Book 119 ABD MSB Acknowledge ACK CycleABC ACK Acknowledge After Every Byte Rule Master ModeArbitration on the Bus Addressing Transfer Formats Master Transmit Sending the Address ByteMaster Receive Master Stop Configuration Slave Mode 31. ACB Register Map ACB Registers32. ACB Registers MASTER. RO Saen Slave Address Enable Reserved Inten Interrupt EnableEN Enable Stop Stop Parallel Port Legacy Functional Blocks33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset 36. Parallel Port Bit Map for Second Level Offset 35. Parallel Port Bit Map for First Level OffsetBits 128 Type Name Uart Functionality SP1 and SP2 39. Bank 1 Register Map 38. Bank Selection Encoding40. Bank 2 Register Map 41. Bank 3 Register Map 43. Bank 1 Bit Map 42. Bank 0 Bit MapRegister Bits Register Bits Offset 45. Bank 3 Bit Map 44. Bank 2 Bit Map132 46. Bank 0 Register Map 3.1 IR/SP3 Mode Register Bank OverviewIRCP/SP3 Register and Bit Maps 01h Register Throughout Offset 00h All Banks 48. Bank 1 Register Map 47. Bank Selection Encoding49. Bank 2 Register Map BSR Bits Bank Selected Functionality 51. Bank 4 Register Map 50. Bank 3 Register Map52. Bank 5 Register Map 54. Bank 7 Register Map 53. Bank 6 Register Map55. Bank 0 Bit Map 57. Bank 2 Bit Map 56. Bank 1 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map 61. Bank 6 Bit Map 60. Bank 5 Bit Map62. Bank 7 Bit Map Feature List Integrated Audio ConfigVideo Processor Interface Low Pin Count LPC Interface Pserial Interface Fast-PCI Interface to External PCI Bus PIO Mode IDE Configuration RegistersIDE Controller Video Retrace Interrupt Physical Region Descriptor Format UltraDMA/33 Mode UltraDMA/33 Signal DefinitionsStop DMARDY# Strobe Ideiordy Sub-ISA Bus Interface Universal Serial BusIOCS0#/IOCS1# Docw Sub-ISA Bus Cycles Sub-ISA Support of Delayed PCI Transactions146 REQ# GNT# 5.4 I/O Recovery DelaysFRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data Steering 148 ISA DMA Cycle Multiplexed PCI / Sub-ISA Balls PCI and Sub-ISA Signal Cycle MultiplexingROM Interface PCI ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# FRAME# TRDY#, IRDY#DMA Controller DMA Channels DMA Controller Registers DMA Transfer ModesDMA Transfer Types DMA Priority DMA Addressing Capability Programmable Interval TimerDMA Page Registers and Extended Addressing DMA Address Generation Programmable Interrupt Controller PIC Interrupt MappingMaster Mapping PIC I/O Registers PIC Interrupt SequencePIC Shadow Register PCI Compatible Interrupts Keyboard Support Fast Keyboard Gate Address 20 and CPU Reset7.1 I/O Port 092h System Control 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Planes vs. Sleep/Global States Power Planes Control Signals vs Sleep StatesPower Management Events Power Button Override Power ButtonThermal Monitoring AMD Geode SC3200 Processor Data Book 159 CPU Power Management Power Management ProgrammingAPM Support Suspend Modulation Save-to-Disk Volt SuspendAMD Geode SC3200 Processor Data Book 161 Device Idle Timers and Traps Peripheral Power ManagementGeneral Purpose Timers Acpi Timer Register Module Power Management SMI Status Reporting RegistersF1BAR0+I/O Power Management Programming Summary Device Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/O Integrated Audio Gpio Interface Byte 11. Physical Region Descriptor FormatAudio Data Buffer Size PRD3 PRD1 PRD2 Codec Command Register Codec Configuration/Control Registers12.2 AC97 Codec Interface Codec Gpio Status and Control Registers VSA Technology Support Hardware Trap SMI Enable RegisterVSA Technology Audio SMI Related Registers Module Core Logic Module Internal IRQ Enable Register IRQ Configuration RegistersInternal IRQ Control Register LPC Interface 12. Cycle Types 13. PCI Configuration Address Register 0CF8h PCI Configuration Space and Access MethodsRegister Descriptions Register Summary Ter’s reset values and page references where the bit forMats are found Core Logic Module Register Summary 32581C Width Reset Reference F0 Index BitsAMD Geode SC3200 Processor Data Book 175 176 32581CCore Logic Module Register Summary 16. F0BAR1 LPC Support Registers Summary 15. F0BAR0 Gpio Support Registers SummaryF0BAR0+ F0BAR1+ F1BAR0+ 18. F1BAR0 SMI Status Registers Summary F1BAR1+ 19. F1BAR1 Acpi Support Registers SummaryAMD Geode SC3200 Processor Data Book 179 180 Width Reset Reference F2 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary Width Reset Reference F3 Index Bits22. F3 PCI Header Registers for Audio Support Summary F2BAR4+ 23. F3BAR0 Audio Support Registers Summary Width ResetF3BAR0+ 182 25. F5BAR0 I/O Control Support Registers Summary Width Reset Reference F5 Index BitsF5BAR0+ AMD Geode SC3200 Processor Data Book 183 Name Reset Value 26. Pciusb USB PCI Configuration Register SummaryPciusb Width Reference Index Bits USBBAR0 27. Usbbar USB Controller Registers SummaryAMD Geode SC3200 Processor Data Book 185 DMA Page Registers Table 28. ISA Legacy I/O Register Summary186 Port Type Name Reference Programmable Interval Timer Registers TableProgrammable Interrupt Controller Registers Table Keyboard Controller Registers Table Bridge, GPIO, and LPC Registers Function Chipset Register SpaceGeneral Remarks Data Parity Detected. This bit is set when Index 06h-07h PCI Status Register R/WAMD Geode SC3200 Processor Data Book 189 Bit Description Index 08h Index 0Eh PCI Header Type RO Reset Value 80hIndex 09h-0Bh Index 0Ch AMD Geode SC3200 Processor Data Book 191 PCI Subtractive Decode Index 42h Reset Control Register R/W Reset Value 01hIndex 43h 192 Index 46h Index 45hIndex 47h AMD Geode SC3200 Processor Data Book 193 Reset Value 7Bh Reset Value FFFFFFFFhPIT Software Reset PIT Counter 1 Enable Generate SMI on A20M# Toggle ROM/AT Logic Control Register R/W Reset Value 98hAMD Geode SC3200 Processor Data Book 195 Index 5Ah Bit Description Index 54h-59hIndex 5Bh Decode Control Register 2 R/W 196 INTA# Ball D26 Target Interrupt INTB# Ball C26 Target InterruptINTD# Ball AA2 Target Interrupt INTC# Ball C9 Target Interrupt 198 Chip Select 1 Positive Decode IOCS1# Index 72hIndex 73h Index 76h 3127 Index 7Ch-7Fh DOCCS# Control Register R/WDiskOnChip Chip Select Positive Decode DOCCS# 200 AMD Geode SC3200 Processor Data Book 201 Index 81h Power Management Enable Register 2 R/W 202 Keyboard/Mouse Access Trap Power Management Enable Register 3 R/W Reset Value 00hParallel/Serial Access Trap AMD Geode SC3200 Processor Data Book 203 Primary Hard Disk Access Trap Floppy Disk Access TrapIndex 83h Power Management Enable Register 4 R/W 204 AMD Geode SC3200 Processor Data Book 205 Index 84h Second Level PME/SMI Status Mirror Register 1 RO 206 AMD Geode SC3200 Processor Data Book 207 208 Index 88h General Purpose Timer 1 Count Register R/W AMD Geode SC3200 Processor Data Book 209 Re-trigger General Purpose Timer 1 on Floppy Disk Activity Index 8Dh Video Speedup Timer Count Register R/W Index 8Bh General Purpose Timer 2 Control Register R/W210 Index 93h Index 8Fh-92hAMD Geode SC3200 Processor Data Book 211 Index 97h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 98h-99h 212 Index A8h-A9h Video Overflow Count Register R/W Index A6h-A7h Video Idle Timer Count Register R/W Index AFh Suspend Notebook Command Register WO Index AEh CPU Suspend Command Register WOIndex B0h-B3h Index B4h Index BAh PIT Shadow Register RO Index B9h PIC Shadow Register ROAMD Geode SC3200 Processor Data Book 215 Reserved. Set to CPU Clock Stop Index BCh Clock Stop Control Register R/W Reset Value 00hIndex BDh-BFh Index C0h-C3h Mask Bit Description Index CChIndex CDh Index CEh Index F4h Index EDh-F3hIndex F5h Second Level PME/SMI Status Register 2 RC 218 AMD Geode SC3200 Processor Data Book 219 Index F6h Second Level PME/SMI Status Register 3 RC 220 Index F7h Second Level PME/SMI Status Register 4 RC Index F8h-FFh I/O mapped registers accessed through F0BAR0 30. F0BAR0+I/O Offset Gpio Configuration RegistersGpio Support Registers Ration registers are located. -29gives the bit formats F0BAR0+I/O Offset 18h is set, this edge generates a PME Offset 14h-17h GPDI1 Gpio Data In 1 Register ROAMD Geode SC3200 Processor Data Book 223 224 Bank AMD Geode SC3200 Processor Data Book 225 LPC Support Registers 31. F0BAR1+I/O Offset LPC Interface Configuration Registers3121 Reserved. Set to AMD Geode SC3200 Processor Data Book 227 228 Serial IRQ Interface Mode Reserved Serial IRQ EnableNumber of IRQ Data Frames AMD Geode SC3200 Processor Data Book 229 230 LPC Game Port 0 Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port 232 Bit 32. F1 PCI Header Registers for SMI Status and Acpi Support SMI Status and Acpi Registers Function SMI Status Support Registers 33. F1BAR0+I/O Offset SMI Status RegistersAMD Geode SC3200 Processor Data Book 235 Offset 02h-03h Top Level PME/SMI Status Register RO/RC Suspend Modulation Enable Mirror. Read to Clear236 AMD Geode SC3200 Processor Data Book 237 238 Offset 04h-05h AMD Geode SC3200 Processor Data Book 239 These addresses should not be written Offset 1Ch-1Fh Offset 0Ah-1Bh240 3124 Offset 24h-27h External SMI Register R/WAMD Geode SC3200 Processor Data Book 241 242 AMD Geode SC3200 Processor Data Book 243 50h-FFh Offset 28h-4Fh Not Used Reset Value 00h244 34. F1BAR1+I/O Offset Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/WAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle 246 1412 1511 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/WOffset 0Ch-0Dh PM1ACNT PM1A Control Register R/W AMD Geode SC3200 Processor Data Book 247 248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 Gpwio Control Register 2 R/W Reset Value 00h Reserved Gpwio Control Register 1 R/W Reset Value 00h252 Offset 17h Gpwio Data Register R/W Reset Value 00h3117 Reserved AMD Geode SC3200 Processor Data Book 253 254 Offset 21h-FFh IDE Controller Registers Function Bit Description Index 30h-3Fh PIOMODE. PIO mode256 Reset Value 00077771h Reset Value 00009172h3024 AMD Geode SC3200 Processor Data Book 257 Index 58h-5Bh Bit Description Index 50h-53hIndex 60h-FFh 258 AMD Geode SC3200 Processor Data Book 259 IDE Controller Support Registers Offset 0Ah Offset 09hOffset 0Bh Offset 0Ch-0Fh Audio Registers Function 37. F3 PCI Header Registers for Audio Configuration Audio Support Registers 38. F3BAR0+Memory Offset Audio Configuration Registers2921 Offset 04h-07h AMD Geode SC3200 Processor Data Book 263 264 AMD Geode SC3200 Processor Data Book 265 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC 266 Reserved. Must be set to Mask Internal IRQ15. Write Only 32581CCore Logic Module Audio Registers FunctionMask Internal IRQ14. Write Only Mask Internal IRQ11. Write Only Mask Internal IRQ3. Write Only Mask Internal IRQ4. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12 270 Bit Description Assert Masked Internal IRQ1 Offset 29h Audio Bus Master 1 SMI Status Register RC Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 2Ah-2Bh Offset 2Ch-2Fh Offset 31h Audio Bus Master 2 SMI Status Register RC Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 32h-33h Offset 34h-37h Offset 39h Audio Bus Master 3 SMI Status Register RC Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 3Ah-3Bh Offset 3Ch-3Fh Offset 41h Audio Bus Master 4 SMI Status Register RC Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 42h-43h Offset 44h-47h Offset 49h Audio Bus Master 5 SMI Status Register RC Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 4Ah-4Bh Offset 4Ch-4Fh 39. F5 PCI Header Registers for X-Bus Expansion Bus Expansion Interface Function Bit Description Index 1Ch-1Fh Core Logic Module X-Bus Expansion Interface Function 32581CIndex 20h-23h Index 24h-27h Index 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 50h-53h F5BAR4 Mask Address Register R/W Index 54h-57h F5BAR5 Mask Address Register R/W AMD Geode SC3200 Processor Data Book 279 Bit Description Index 64h-67h 40. F5BAR0+I/O Offset X-Bus Expansion Registers Base address that allows PCI access to additional I/O ConBus Expansion Support Registers F5 Index 10h, Base Address Register 0 F5BAR0 set Iostrapidselselect Idsel Strap Override Iotestporten Debug Test Port EnableAMD Geode SC3200 Processor Data Book 281 USB Controller Registers Pciusb 41. Pciusb USB PCI Configuration RegistersBit Description 282 Index 0Dh Latency Timer Register R/W Reset Value 08hCore Logic Module USB Controller Registers Pciusb 32581C Index 06h-07h Status Register R/W Reset Value A0F8h Reset Value 0E11hReset Value 50h Index 30h-3Bh AMD Geode SC3200 Processor Data Book 285 42. USBBAR+Memory Offset USB Controller Registers OwnershipChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hRootHubStatusChangeEnable FrameNumberOverflowEnable 287 Offset 28h-2Bh Reset Value = 01000003h Reset Value = 00000628hBit Description Offset 34h-37h Offset 38h-3Bh Offset 50h-53h HcRhStatus Register R/W Read LocalPowerStatusChange. Not supported. Always read3018 AMD Geode SC3200 Processor Data Book 289 Read PortResetStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortSuspendStatus 290 AMD Geode SC3200 Processor Data Book Read CurrentConnectStatus Bit Description Read PortEnableStatus1510 AMD Geode SC3200 Processor Data Book 291 292 Offset 60h-9Fh Reset Value = xxhOffset 100h-103h 319 Reserved. Read/Write 0s Offset 104h-107h Reset Value = 000000xxh318 Reserved. Read/Write 0s 294 43. DMA Channel Control Registers ISA Legacy Register Space Timing Mode Priority Mode32581CCore Logic Module ISA Legacy Register Space Write Channel Number Mode Select Transfer ModeBit Description Port 00Bh Address Direction Undefined Write DMA Command Register, Channels298 Port 0D4h Bit Description Port 0D2hPort 0D6h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Bit Description Port 042h Write Current Counter Mode BCD ModeCounter Value Read Port 043h R/W 46. Programmable Interrupt Controller Registers Register Read Mode Poll CommandBit Description IRQ2 / IRQ10 Mask IRQ1 / IRQ9 Mask IRQ6 / IRQ14 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 49. Miscellaneous Registers 48. Real-Time Clock Registers 308 Video Input Port VIP General FeaturesHardware Video Acceleration Graphics-Video Overlay and Blending Mixer/Blender VIP Video Support Functional DescriptionVBI Support AMD Geode SC3200 Processor Data Book 311 Active Video Video Input Port VIP Direct Video ModeGenLock Bob Capture Video ModeProgram the VIP bus master address registers Program other VIP bus master support registers AMD Geode SC3200 Processor Data Book 315 Weave Ping-pongs between the two buffers during runtime Field Interrupt Capture VBI Mode316 Video Input Formatter Video BlockLine Buffer AMD Geode SC3200 Processor Data Book 317 Filtering Horizontal Downscaler with 4-Tap FilteringHorizontal Downscaler Formatter Line Buffers2.5 2-Tap Vertical and Horizontal Upscalers AMD Geode SC3200 Processor Data Book 319 RGB Mixer/Blender BlockRAM YUV YUV to RGB CSC in Video Data Path Valid Mixing/Blending ConfigurationsGamma Correction Color/Chroma Key Graphics Window Color/Chroma Key and Mixer/BlenderVideo Window Cursor Window Mixing/Blending Operation Truth Table for Alpha BlendingColor CHROMASEL1 324 12. Color Key and Alpha Blending Logic TFT Interface Power SequenceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1 326 Integrated PLL F4 PCI Header Registers for Video Processor Support Summary F4BAR0 Video Processor Configuration Registers SummaryF4BAR0+ 328 32581CVideo Processor Module Register Summary F4BAR2+ F4BAR2 VIP Support Registers SummaryAMD Geode SC3200 Processor Data Book 329 Reset Value 030000h Reset Value 0504hVideo Processor Registers Function 3112 VIP Base Address 110 Address Range. Read Only AMD Geode SC3200 Processor Data Book 331 Index 3Eh-FFh Reserved EN42X Enable 42x Format. Allows format selection Video Configuration Register R/W Reset Value 00000000hVideo Processor Support Registers F4BAR0 To 0 or 1 should be written with a value that is read Reserved. Write as read Reserved Offset 04h-07h Display Configuration Register R/WAMD Geode SC3200 Processor Data Book 333 334 Bit Description Offset 08h-0Bh Video X Position Register R/W Offset 20h-23h Bit Description Offset 14h-17h Video Color Key Register R/W Reserved PLL2PWREN PLL2 Power-Down Enable Reset Value 00001400hBit Description Offset 28h-2Bh Clkdivsel Clock Divider Select DTS Downscale Type Select Reserved Signen Signature EnableOffset 40h-43h Video Downscaler Coefficient Register R/W FLTCO4 Filter Coefficient 4. For the tap-4 filter 338 Reserved Set to Offset 54h-57h Offset 50h-53hAMD Geode SC3200 Processor Data Book 339 340 Enable Alpha Window Disable Alpha Window 158 AMD Geode SC3200 Processor Data Book 341 342 Offset 94h-97h Bit Description Offset 90h-93hALPHA3VAL Value for Alpha Window ALPHA2VAL Value for Alpha Window Ctgenlocken Enable Continuous GenLock Function Reserved. Set to Genlocktouten GenLock Timeout EnableReserved. Set to Offset 424h-427h 3121 Reserved 200 VIP Support Registers F4BAR2 F4BAR2+Memory Offset VIP Configuration RegistersF4 Index 18h, Base Address Register 2 F4BAR2 points to AMD Geode SC3200 Processor Data Book 345 Capture Store to Memory Video Data Capture Store to Memory VBI DataReserved. Read Only Current Field. Read Only 2322 Run Status. Read Only Bit Description Video Data Capture Active. Read Only3110 Reserved Start of each field Offset 14h-17h Offset 48h-4Bh VBI Data Pitch Register R/W Offset 44h-47h VBI Data Even Base Register R/W Testability Jtag Jtag Mode Instruction SupportMandatory Instruction Support Optional Instruction Support 350 Power/Ground Connections and Decoupling General SpecificationsElectro Static Discharge ESD Absolute Maximum Ratings Operating Conditions Symbol Parameter Min Typ Max Unit CommentsVSS Power Plane Signal Names VCC Balls VSS Balls Power Planes of External Interface SignalsPower State Parameter Definitions DC Current DC Characteristics for On State Symbol ParameterNote Min Typ Max Unit Comments DC Characteristics for Active Idle, Sleep, and Off StatesBall Capacitance and Inductance Balls with PU/PD Resistors Pull-Up and Pull-Down ResistorsVIO External PU or PD resistor Symbol Description Reference DC CharacteristicsWire 10. Buffer Types Inbtn DC Characteristics Inab DC CharacteristicsInpci DC Characteristics INT DC Characteristics Instrp DC CharacteristicsInts DC Characteristics INTS1 DC Characteristics ODn DC Characteristics Inusb DC Characteristics Op/n DC Characteristics Odpci DC CharacteristicsOpci DC Characteristics Ousb DC Characteristics 11. Default Levels for Measurement Switching Parameters AC CharacteristicsSymbol Parameter Value CLK Outputs Memory Controller InterfaceInputs 12. Memory Controller Timing Parameters 32581CElectrical SpecificationsSDCLK30, Sdclkout high time 233 MHz 266 MHz 364 SDCLK30 Control Output, MA120 T1, t2, t3BA10, MD630 MD630 Data Valid Read Data Vpckin Vref Video Port 13. Video Input Port Timing Parameters Tftdck rise/fall time between 0.8V TFT Interface 14. TFT Timing ParametersTftdck period time multiplexed on IDE Tftdck period time multiplexed on 15. ACCESS.bus Input Timing Parameters ACCESS.bus Interface16. ACCESS.bus Output Timing Parameters AB1C AB2C AB1D AB2D AB1D AB2D AB1C AB1D AB2D AB1C AB2C370 PCI Bus Interface 17. PCI AC Specifications 64VIO 16VIOEquation a Equation B Pciclk 0.4 V IO 18. PCI Clock Parameters 19. PCI Timing Parameters 20. Measurement Condition Parameters Symbol Value Unit CommentsMeasurement and Test Conditions Signals PowerInput Valid Ms typ Sub-ISA Interface Symbol Parameter Bits Type Comments21. Sub-ISA Timing Parameters Bus Width Min DOCR#/IOR# Bus Width Min Max Symbol Parameter Bits Type Comments IOR#/RD#/TRDE# ROMCS#/DOCCS#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW# IOCS10# DOCCS#/ROMCS#IOW#/WR# MEMW#/DOCW# TRDE# D150 LPC Interface 22. LPC and Serirq Timing Parameters IDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE Interface 23. IDE General Timing Parameters IDERST# pulse width 24. IDE Register Transfer to/from Device Timing Parameters Mode Symbol Parameter Unit CommentsCycle time min Width 8-bit min IDEIOR0# IDEIOW0# Write IDEDATA70 Addr valid1Read IDEDATA70 IDEIORDY0 2,3 AMD Geode SC3200 Processor Data Book 385 25. IDE PIO Data Transfer to/from Device Timing Parameters Read IDEDATA150 IDEIOR0# IDEIOW0# Write IDEDATA150386 26. IDE Multiword DMA Data Transfer Timing Parameters IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# IDECS10#388 27. IDE UltraDMA Data Burst Timing Parameters Mode Symbol Parameter Min Max Unit CommentsAMD Geode SC3200 Processor Data Book 389 STOP0 IDEREQ0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0 IDEDATA150 at device IDEIRDY0 DSTROBE0 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at host AMD Geode SC3200 Processor Data Book 391 IDEIOW0STOP0 host IDEDREQ0 device IDEDACK0 hostIDEIOR0HDMARDY0 392 IDEIOW0# STOP0# IDEDREQ0 deviceAMD Geode SC3200 Processor Data Book 393 IDEIRDY0 DSTROBE0 device IDEDATA150 device IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDECS01# IDEADDR20 IDEIOW0# STOP0# host DevicetUI IDEDACK0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# host At host HSTROBE0#IDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at device IDEIORDY0# DDMARDY0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIOR0# HSTROBE0# AMD Geode SC3200 Processor Data Book 397 IDEDATA150 host IDEADDR20 IDECS01# IDEIORDY0# DDMARDY0# device398 IDEDATA150 host IDECS01# IDEADDR20 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostAMD Geode SC3200 Processor Data Book 399 Low Speed Source Note Full Speed Receiver EOP Width Note Host upstream Source EOP widthReceiver data jitter tolerance for paired Low Speed Receiver EOP Width Note Differential Data Lines Rise Time Fall TimeDifferential Data Lines Crossover Points 2.0 Consecutive Transitions Data Crossover Level Differential Data to SE0 SkewEOP Width Differential Crossover Points Data Lines TCPN + Transmitter Sharp-IR and Consumer Remote Control Modulation signal periodSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg register MIR Fast IR Port 30. Fast IR Port Timing ParametersFIR STB# Busy ACK# 32. Enhanced Parallel Port Timing Parameters Symbol Parameter MinUnit Comments Extended Capabilities Port ECP 33. ECP Forward Mode Timing ParametersAFD# Busy BUSY# 34. ECP Reverse Mode Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delay Audio Interface AC97 35. AC Reset Timing ParametersSync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width AC97CLK Vold 37. AC97 Clocks Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 38. AC97 I/O Timing Parameters 39. AC97 Signal Rise and Fall Timing Parameters End of Slot 2 to Bitclk Sdatain low 40. AC97 Low Power Mode Timing ParametersSlot Bitclk Sdataout Power management event to ONCTL# Assertion Power Management Interface41. PWRBTN# Timing Parameters ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# AMD Geode SC3200 Processor Data Book 417 POR# 32KHZ Non-test inputs setup time TDI, TMS setup timeJtag Interface 45. Jtag Timing Parameters TDI, TMS hold time Input Signals Output SignalsTDI TMS TDO AMD Geode SC3200 Processor Data Book 419 420 ΘJC ×C/W Thermal CharacteristicsCase-to-Ambient Thermal Resistance Example @ 85C Example Heatsink ConsiderationsAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C Therefore AMD Geode SC3200 Processor Data Book 423 Physical Dimensions 424 BGU481 Package Bottom View Ordering Part Number Core Frequency Order InformationMHz Degree C Package Table A-1. Revision History Data Book Revision HistoryRevision # Revisions / Comments Appendix a Data Book Revision History 32581C 89V toAMD Geode SC3200 Processor Data Book 427