Integrated Audio, Video Processor Interface, Config

	32581C			Core Logic Module

Integrated Audio		6.2		Module Architecture
• AC97 Version 2.0 compliant interface to audio codecs		The Core Logic architecture provides the internal functional
•	Secondary codec support	blocks shown in Figure 6-1.
		• Fast-PCI interface to external PCI bus
•	AMC97 codec support
		• IDE controllers (UDMA-33)

Video Processor Interface		•	USB controllers

• Synchronous serial interface to the Video Processor		• Sub-ISA bus interface

• Translates video and clock control register accesses		• AT compatibility logic (legacy)
	from PCI to serial interface

• Supports both reads and writes of Video Processor		• ACPI compliant power management (includes GPIO
			interfaces, such as joystick)
	registers

• Retries Fast-PCI bus accesses until Core Logic		•	Integrated audio controller

	completes the transfer over the serial interface	• Low Pin Count (LPC) Interface

Low Pin Count (LPC) Interface

•Based on Intel LPC Interface Specification Revision 1.0

•Serial IRQ support

Fast-PCI

UDMA33

IDE

33-66 MHz

PCI

Fast X-Bus

PCI Interface

33 MHz

USB

Config.

USB

Reg.

X-Bus

Audio

AC97

Controller

GPIOs

ACPI/PM

LPC

Legacy

ISA/PIC/PIT/DMA

GPIOs

LPC Sub-ISA

Figure 6-1. Core Logic Module Block Diagram

140	AMD Geode™ SC3200 Processor Data Book

Page 140

Image 140

AMD SC3200 Integrated Audio, Video Processor Interface, Low Pin Count LPC Interface, Config, Reg, Controller GPIOs, Legacy

Contents

Publication ID 32581C AMD Geode SC3200 Processor Data Book Advanced Micro Devices, Inc. All rights reserved Contacts Trademarks Contents Electrical Specifications Package SpecificationsCore Logic Module Video Processor Module Power Supply Connections Typical Battery ConfigurationTypical Battery Current Normal Operation Mode ACCESS.bus Data Transaction Multiword DMA Data Transfer Timing Diagram 388 Fast IR MIR and FIR Timing Diagram 405316 360 410 411412 413 32581C Serial Ports 1 and 2 Configuration Register ACB1 and ACB2 Configuration RegisterParallel Port Configuration Register System Power States Banks 0 and 1 Common Control and Status Registers 116 117164 165 Pciusb USB PCI Configuration Register Summary F0BAR0+I/O Offset Gpio Configuration RegistersF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration 383 385387 Jtag Timing Parameters 418 QJC ×C/W 421 General Description Video ProcessorCore Logic SuperI/O Features General FeaturesGX1 Processor Module Video Processor Module SuperI/O Module Other FeaturesNand Eeprom 32581C Architecture Overview 32581C GX1 ModuleMemory Controller SC3200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Register Summary MCMEMCNTRL2 R/W Bit Description GXBASE+8408h-840Bh Mcbankcfg R/WRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdracc R/W Mcgbaseadd R/WMcdradd R/W Fast-PCI Bus Display1 GX1 Module Interface Video Input Port Clock, Timers, and Reset Logic Reset LogicPower-On Reset System Reset 32581C ACCESS.bus SystemInterface Memory USB Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball Number RD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 Signal Name Ball No BGU481 Ball Assignment Sorted Alphabetically by Signal Name32581CSignal Definitions FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options Multiplexing Configuration Two-Signal/Group MultiplexingDefault Alternate Ball No Signal Configuration TFT, PCI, GPIO, System Three-Signal/Group Multiplexing ACCESS.busInternal Test AC97 Fpci Monitoring Gpio PCI2 TFT3AB1 Gpio IDE2 Four-Signal/Group Multiplexing Signal Descriptions Signal Name Ball No Type Description MuxMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enables Memory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKE Video Port Interface Signals Video Port Clock Input. The clock input from TFT Interface Signals ACCESS.bus Interface Signals Multiplexed Address and Data. a bus transaction con PCI Bus Interface SignalsMultiplexed Command and Byte Enables. During FRAME# IRDY#TRDY# STOP# LOCK# DEVSEL#BHE# SERR# REQ1# REQ0#VIP USB Sub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface SignalsIDE Chip Selects 0 and 1. These signals are used to IDE I/O Read Channels 0 and 1. IDEIOR0# is the read Universal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals Data Terminal Ready Outputs. When low, indicate to Parallel Port Interface Signals Fast Infrared IR Port Interface Signals STB#/WRITE#FFRAME# IRRX1 AK8 14 AC97 Audio Interface Signals Serial Bus Synchronization. This bit is asserted to syn Power Management Interface Signals General Purpose Wakeup I/Os. These signals eachSuspend Power Plane Control 1 and 2. Control signal KHz Output Clock Gpio Interface Signals Debug Monitoring Interface Signals Jtag Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input to Test and Measurement Interface Signals PLL6, PLL5 and PLL2 Bypass. These signals are usedMemory Internal Test Signals. These signals are used Thermal Diode Positive / Negative. These signals are Power, Ground and No Connections1 Configuration Block Addresses General Configuration Block Register SummaryGeneral Configuration Block 32581C Offset Width Bits Type Name Reset Value Reference Ball # Internal Test Signals Name Add’l Dependencies Other Signal Add’l DependenciesPMR27 Fpcimon Ball # IDE Signals Gpio and TFT Signals Name TFT Name Add’l Dependencies BitPP/ACB1/FPCI Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to 32581CGeneral Configuration Block Reserved Bit Description Interrupt Selection Register Intsel R/W Reset Value 00h Reset Value xxhOffset 39h-3Bh Offset 3Ch Watchdog Timer Functional Description Watchdog Registers Watchdog Interrupt3describes the Watchdog registers Usage Hints High-Resolution Timer High-Resolution Timer RegistersWatchdog Status Register Wdsts R/WC Reset Value 00h Offset 05h-07h Reset Value xxxxxxxxh Tmclksel Timer Clock SelectTmen Timer Interrupt Enable Bit Description Offset 08h-0Bh Clock Generation Block Diagram Clock Generators and PLLs Component Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components 2 GX1 Module Core Clock Internal Fast-PCI ClockCore Clock Frequency Strapped Core Clock Frequency Video Processor Clocks SuperI/O ClocksCore Logic Module Clocks 8describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 1514 AB1C AB1D AB2C AB2D Outstanding FeaturesISA PC98 and Acpi Compliant Serial PortSerial Port 3 / Infrared IR Communication Port System Wakeup Control SWC Module Architecture AccessInternal Internal Signals Configuration Structure / Access SIO Configuration OptionsIndex-Data Register Pair LDN Assignments Default Configuration Setup Address Decoding Standard Configuration Registers SIO Control and Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers DMA Channel Select 1 R/W Index F0h-FEh Logical Device Configuration R/W32581CSuperI/O Module SIO Control and Configuration Registers SIO Control and Configuration Register MapIndex Type Name Power Rail Reset Value SID. SIO ID Logical Device Control and Configuration Relevant RTC Configuration Registers RTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers 12. Serial Ports 1 and 2 Configuration Register Serial Ports 1 and 2 Configuration register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 1 14. ACB1 and ACB2 Configuration Register LDN 05h and 06h ACCESS.bus Ports 1ACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers 16. Parallel Port Configuration Register 15. Relevant Parallel Port Registers X32I External X32O Battery = 0.1 μF Real-Time Clock RTCBus Interface RTC Clock Generation Signal Parameters External ElementsOscillator Startup External Oscillator Alarms Timekeeping Data FormatDaylight Saving Leap Years BT1 Power SupplyRTC 18. System Power States 108 Battery-Backed RAMs and RegistersInterrupt Handling RTC Registers 19. RTC Register Map20. RTC Registers Index Type Name 110 Index 05h Hours Alarm Register Hora R/WIndex 04h Hours Register HOR R/W Index Programmable Month Alarm Register Mona R/W Index 0Ch RTC Control Register C CRC ROIndex Programmable Century Register CEN R/W AMD Geode SC3200 Processor Data Book 111 21. Divider Chain Control / Test Selection 22. Periodic Interrupt Rate Encoding23. BCD and Binary Formats Rate Select Periodic Interrupt Divider Rate ms Chain Output 0Eh 7Fh Battery-backed general-purpose Byte RAM 00h 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM Map 26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection SWC Registers 27. Banks 0 and 1 Common Control and Status Register MapType Name Value Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bit Description Ceir Wakeup Range 1 Registers Bank 1, Offset 0Ah IRWTR1L Register R/WCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 Registers ACCESS.bus Interface Data TransactionsABD ABC AMD Geode SC3200 Processor Data Book 119 ABC ACK Acknowledge ACK CycleABD MSB Master Mode Acknowledge After Every Byte RuleArbitration on the Bus Addressing Transfer Formats Sending the Address Byte Master TransmitMaster Receive Master Stop Slave Mode Configuration 32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO Reserved Inten Interrupt Enable Saen Slave Address EnableEN Enable Stop Stop Legacy Functional Blocks Parallel Port33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset 35. Parallel Port Bit Map for First Level Offset 36. Parallel Port Bit Map for Second Level OffsetBits 128 Uart Functionality SP1 and SP2 Type Name 38. Bank Selection Encoding 39. Bank 1 Register Map40. Bank 2 Register Map 41. Bank 3 Register Map 42. Bank 0 Bit Map 43. Bank 1 Bit MapRegister Bits Register Bits Offset 132 44. Bank 2 Bit Map45. Bank 3 Bit Map 3.1 IR/SP3 Mode Register Bank Overview 46. Bank 0 Register MapIRCP/SP3 Register and Bit Maps 01h Register Throughout Offset 00h All Banks 47. Bank Selection Encoding 48. Bank 1 Register Map49. Bank 2 Register Map BSR Bits Bank Selected Functionality 52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 56. Bank 1 Bit Map 57. Bank 2 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map 62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Config Integrated AudioVideo Processor Interface Low Pin Count LPC Interface Fast-PCI Interface to External PCI Bus Pserial Interface IDE Configuration Registers PIO ModeIDE Controller Video Retrace Interrupt Physical Region Descriptor Format UltraDMA/33 Signal Definitions UltraDMA/33 ModeStop DMARDY# Strobe Ideiordy Universal Serial Bus Sub-ISA Bus InterfaceIOCS0#/IOCS1# Docw 146 Sub-ISA Support of Delayed PCI TransactionsSub-ISA Bus Cycles 5.4 I/O Recovery Delays REQ# GNT#FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data Steering ISA DMA 148 PCI and Sub-ISA Signal Cycle Multiplexing Cycle Multiplexed PCI / Sub-ISA BallsROM Interface PCI FRAME# TRDY#, IRDY# ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#DMA Controller DMA Channels DMA Transfer Modes DMA Controller RegistersDMA Transfer Types DMA Priority Programmable Interval Timer DMA Addressing CapabilityDMA Page Registers and Extended Addressing DMA Address Generation PIC Interrupt Mapping Programmable Interrupt ControllerMaster Mapping PIC Interrupt Sequence PIC I/O RegistersPIC Shadow Register PCI Compatible Interrupts Fast Keyboard Gate Address 20 and CPU Reset Keyboard Support7.1 I/O Port 092h System Control 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States Power Button Power Button OverrideThermal Monitoring AMD Geode SC3200 Processor Data Book 159 Power Management Programming CPU Power ManagementAPM Support Suspend Modulation AMD Geode SC3200 Processor Data Book 161 Volt SuspendSave-to-Disk Peripheral Power Management Device Idle Timers and TrapsGeneral Purpose Timers Acpi Timer Register F1BAR0+I/O Power Management SMI Status Reporting RegistersModule Device Power Management Programming Summary Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/O Gpio Interface Integrated Audio 11. Physical Region Descriptor Format ByteAudio Data Buffer Size PRD1 PRD2 PRD3 Codec Configuration/Control Registers Codec Command Register12.2 AC97 Codec Interface Codec Gpio Status and Control Registers Trap SMI Enable Register VSA Technology Support HardwareVSA Technology Audio SMI Related Registers Module Core Logic Module IRQ Configuration Registers Internal IRQ Enable RegisterInternal IRQ Control Register LPC Interface 12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary AMD Geode SC3200 Processor Data Book 175 Width Reset Reference F0 Index BitsCore Logic Module Register Summary 32581C 32581CCore Logic Module Register Summary 176 15. F0BAR0 Gpio Support Registers Summary 16. F0BAR1 LPC Support Registers SummaryF0BAR0+ F0BAR1+ 18. F1BAR0 SMI Status Registers Summary F1BAR0+ AMD Geode SC3200 Processor Data Book 179 19. F1BAR1 Acpi Support Registers SummaryF1BAR1+ Width Reset Reference F2 Index Bits 180 Width Reset Reference F3 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary22. F3 PCI Header Registers for Audio Support Summary F2BAR4+ Width Reset 23. F3BAR0 Audio Support Registers SummaryF3BAR0+ 182 Width Reset Reference F5 Index Bits 25. F5BAR0 I/O Control Support Registers SummaryF5BAR0+ AMD Geode SC3200 Processor Data Book 183 26. Pciusb USB PCI Configuration Register Summary Name Reset ValuePciusb Width Reference Index Bits AMD Geode SC3200 Processor Data Book 185 27. Usbbar USB Controller Registers SummaryUSBBAR0 186 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Programmable Interval Timer Registers Table Port Type Name ReferenceProgrammable Interrupt Controller Registers Table Keyboard Controller Registers Table General Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function AMD Geode SC3200 Processor Data Book 189 Index 06h-07h PCI Status Register R/WData Parity Detected. This bit is set when Index 0Eh PCI Header Type RO Reset Value 80h Bit Description Index 08hIndex 09h-0Bh Index 0Ch PCI Subtractive Decode AMD Geode SC3200 Processor Data Book 191 Reset Control Register R/W Reset Value 01h Index 42hIndex 43h 192 Index 45h Index 46hIndex 47h AMD Geode SC3200 Processor Data Book 193 Reset Value FFFFFFFFh Reset Value 7BhPIT Software Reset PIT Counter 1 Enable AMD Geode SC3200 Processor Data Book 195 ROM/AT Logic Control Register R/W Reset Value 98hGenerate SMI on A20M# Toggle Bit Description Index 54h-59h Index 5AhIndex 5Bh Decode Control Register 2 R/W 196 INTB# Ball C26 Target Interrupt INTA# Ball D26 Target InterruptINTD# Ball AA2 Target Interrupt INTC# Ball C9 Target Interrupt 198 Index 72h Chip Select 1 Positive Decode IOCS1#Index 73h Index 76h Index 7Ch-7Fh DOCCS# Control Register R/W 3127DiskOnChip Chip Select Positive Decode DOCCS# 200 Index 81h Power Management Enable Register 2 R/W AMD Geode SC3200 Processor Data Book 201 202 Power Management Enable Register 3 R/W Reset Value 00h Keyboard/Mouse Access TrapParallel/Serial Access Trap AMD Geode SC3200 Processor Data Book 203 Floppy Disk Access Trap Primary Hard Disk Access TrapIndex 83h Power Management Enable Register 4 R/W 204 Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC3200 Processor Data Book 205 206 AMD Geode SC3200 Processor Data Book 207 Index 88h General Purpose Timer 1 Count Register R/W 208 Re-trigger General Purpose Timer 1 on Floppy Disk Activity AMD Geode SC3200 Processor Data Book 209 210 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W AMD Geode SC3200 Processor Data Book 211 Index 8Fh-92hIndex 93h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/W Index 97hIndex 98h-99h 212 Index A6h-A7h Video Idle Timer Count Register R/W Index A8h-A9h Video Overflow Count Register R/W Index AEh CPU Suspend Command Register WO Index AFh Suspend Notebook Command Register WOIndex B0h-B3h Index B4h AMD Geode SC3200 Processor Data Book 215 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Index BCh Clock Stop Control Register R/W Reset Value 00h Reserved. Set to CPU Clock StopIndex BDh-BFh Index C0h-C3h Bit Description Index CCh MaskIndex CDh Index CEh Index EDh-F3h Index F4hIndex F5h Second Level PME/SMI Status Register 2 RC 218 Index F6h Second Level PME/SMI Status Register 3 RC AMD Geode SC3200 Processor Data Book 219 Index F7h Second Level PME/SMI Status Register 4 RC 220 Index F8h-FFh 30. F0BAR0+I/O Offset Gpio Configuration Registers I/O mapped registers accessed through F0BAR0Gpio Support Registers Ration registers are located. -29gives the bit formats AMD Geode SC3200 Processor Data Book 223 Offset 14h-17h GPDI1 Gpio Data In 1 Register ROF0BAR0+I/O Offset 18h is set, this edge generates a PME Bank 224 AMD Geode SC3200 Processor Data Book 225 31. F0BAR1+I/O Offset LPC Interface Configuration Registers LPC Support Registers3121 Reserved. Set to AMD Geode SC3200 Processor Data Book 227 228 Reserved Serial IRQ Enable Serial IRQ Interface ModeNumber of IRQ Data Frames AMD Geode SC3200 Processor Data Book 229 230 LPC Game Port 1 Address Select. Selects I/O Port LPC Game Port 0 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port 232 Bit SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support AMD Geode SC3200 Processor Data Book 235 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers 236 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC AMD Geode SC3200 Processor Data Book 237 Offset 04h-05h 238 AMD Geode SC3200 Processor Data Book 239 240 Offset 0Ah-1BhThese addresses should not be written Offset 1Ch-1Fh AMD Geode SC3200 Processor Data Book 241 Offset 24h-27h External SMI Register R/W3124 242 AMD Geode SC3200 Processor Data Book 243 244 Offset 28h-4Fh Not Used Reset Value 00h50h-FFh Offset 06h Smicmd OS/BIOS Requests Register R/W 34. F1BAR1+I/O Offset Acpi Support RegistersAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle 1412 246 Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W 1511Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W AMD Geode SC3200 Processor Data Book 247 248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 252 Gpwio Control Register 1 R/W Reset Value 00hGpwio Control Register 2 R/W Reset Value 00h Reserved Gpwio Data Register R/W Reset Value 00h Offset 17h3117 Reserved AMD Geode SC3200 Processor Data Book 253 Offset 21h-FFh 254 IDE Controller Registers Function 256 PIOMODE. PIO modeBit Description Index 30h-3Fh Reset Value 00009172h Reset Value 00077771h3024 AMD Geode SC3200 Processor Data Book 257 Bit Description Index 50h-53h Index 58h-5BhIndex 60h-FFh 258 IDE Controller Support Registers AMD Geode SC3200 Processor Data Book 259 Offset 09h Offset 0AhOffset 0Bh Offset 0Ch-0Fh 37. F3 PCI Header Registers for Audio Configuration Audio Registers Function 38. F3BAR0+Memory Offset Audio Configuration Registers Audio Support Registers2921 Offset 04h-07h AMD Geode SC3200 Processor Data Book 263 264 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC AMD Geode SC3200 Processor Data Book 265 266 Reserved. Must be set to 32581CCore Logic Module Audio Registers Function Mask Internal IRQ15. Write OnlyMask Internal IRQ14. Write Only Mask Internal IRQ11. Write Only Mask Internal IRQ4. Write Only Mask Internal IRQ3. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12 Bit Description Assert Masked Internal IRQ1 270 Audio Bus Master 1 Command Register R/W Reset Value 00h Offset 29h Audio Bus Master 1 SMI Status Register RCOffset 2Ah-2Bh Offset 2Ch-2Fh Audio Bus Master 2 Command Register R/W Reset Value 00h Offset 31h Audio Bus Master 2 SMI Status Register RCOffset 32h-33h Offset 34h-37h Audio Bus Master 3 Command Register R/W Reset Value 00h Offset 39h Audio Bus Master 3 SMI Status Register RCOffset 3Ah-3Bh Offset 3Ch-3Fh Audio Bus Master 4 Command Register R/W Reset Value 00h Offset 41h Audio Bus Master 4 SMI Status Register RCOffset 42h-43h Offset 44h-47h Audio Bus Master 5 Command Register R/W Reset Value 00h Offset 49h Audio Bus Master 5 SMI Status Register RCOffset 4Ah-4Bh Offset 4Ch-4Fh Bus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus Expansion Core Logic Module X-Bus Expansion Interface Function 32581C Bit Description Index 1Ch-1FhIndex 20h-23h Index 24h-27h Index 48h-4Bh F5BAR2 Mask Address Register R/W Index 4Ch-4Fh F5BAR3 Mask Address Register R/WIndex 50h-53h F5BAR4 Mask Address Register R/W Index 54h-57h F5BAR5 Mask Address Register R/W Bit Description Index 64h-67h AMD Geode SC3200 Processor Data Book 279 Base address that allows PCI access to additional I/O Con 40. F5BAR0+I/O Offset X-Bus Expansion RegistersBus Expansion Support Registers F5 Index 10h, Base Address Register 0 F5BAR0 set AMD Geode SC3200 Processor Data Book 281 Iotestporten Debug Test Port EnableIostrapidselselect Idsel Strap Override 41. Pciusb USB PCI Configuration Registers USB Controller Registers PciusbBit Description 282 Reset Value 08h Index 0Dh Latency Timer Register R/WCore Logic Module USB Controller Registers Pciusb 32581C Index 06h-07h Status Register R/W Reset Value 0E11h Reset Value A0F8hReset Value 50h Index 30h-3Bh 42. USBBAR+Memory Offset USB Controller Registers AMD Geode SC3200 Processor Data Book 285 HcInterruptEnable Register R/W Reset Value = 00000000h OwnershipChangeEnableRootHubStatusChangeEnable FrameNumberOverflowEnable Offset 28h-2Bh 287 Reset Value = 00000628h Reset Value = 01000003hBit Description Offset 34h-37h Offset 38h-3Bh Read LocalPowerStatusChange. Not supported. Always read Offset 50h-53h HcRhStatus Register R/W3018 AMD Geode SC3200 Processor Data Book 289 HcRhPortStatus1 Register R/W Reset Value = 00000000h Read PortResetStatusRead PortSuspendStatus 290 AMD Geode SC3200 Processor Data Book Bit Description Read PortEnableStatus Read CurrentConnectStatus1510 AMD Geode SC3200 Processor Data Book 291 292 Reset Value = xxh Offset 60h-9FhOffset 100h-103h 319 Reserved. Read/Write 0s Reset Value = 000000xxh Offset 104h-107h318 Reserved. Read/Write 0s 294 ISA Legacy Register Space 43. DMA Channel Control Registers Priority Mode Timing Mode32581CCore Logic Module ISA Legacy Register Space Write Transfer Mode Channel Number Mode SelectBit Description Port 00Bh Address Direction 298 Write DMA Command Register, ChannelsUndefined Bit Description Port 0D2h Port 0D4hPort 0D6h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Current Counter Mode BCD Mode Bit Description Port 042h WriteCounter Value Read Port 043h R/W 46. Programmable Interrupt Controller Registers Poll Command Register Read ModeBit Description IRQ2 / IRQ10 Mask IRQ1 / IRQ9 Mask Interrupt Service Register IRQ7 / IRQ15 In-Service IRQ6 / IRQ14 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers 308 General Features Video Input Port VIPHardware Video Acceleration Graphics-Video Overlay and Blending VIP Mixer/Blender Functional Description Video SupportVBI Support AMD Geode SC3200 Processor Data Book 311 Active Video GenLock Direct Video ModeVideo Input Port VIP Capture Video Mode BobProgram the VIP bus master address registers Program other VIP bus master support registers Weave AMD Geode SC3200 Processor Data Book 315 316 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime Video Block Video Input FormatterLine Buffer AMD Geode SC3200 Processor Data Book 317 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering Line Buffers Formatter2.5 2-Tap Vertical and Horizontal Upscalers AMD Geode SC3200 Processor Data Book 319 Mixer/Blender Block RGBRAM YUV Valid Mixing/Blending Configurations YUV to RGB CSC in Video Data PathGamma Correction Color/Chroma Key Color/Chroma Key and Mixer/Blender Graphics WindowVideo Window Cursor Window Truth Table for Alpha Blending Mixing/Blending OperationColor CHROMASEL1 12. Color Key and Alpha Blending Logic 324 Power Sequence TFT InterfaceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1 Integrated PLL 326 F4BAR0+ F4BAR0 Video Processor Configuration Registers SummaryF4 PCI Header Registers for Video Processor Support Summary 32581CVideo Processor Module Register Summary 328 AMD Geode SC3200 Processor Data Book 329 F4BAR2 VIP Support Registers SummaryF4BAR2+ Reset Value 0504h Reset Value 030000hVideo Processor Registers Function 3112 VIP Base Address 110 Address Range. Read Only Index 3Eh-FFh Reserved AMD Geode SC3200 Processor Data Book 331 Video Configuration Register R/W Reset Value 00000000h EN42X Enable 42x Format. Allows format selectionVideo Processor Support Registers F4BAR0 To 0 or 1 should be written with a value that is read AMD Geode SC3200 Processor Data Book 333 Offset 04h-07h Display Configuration Register R/WReserved. Write as read Reserved Bit Description Offset 08h-0Bh Video X Position Register R/W 334 Bit Description Offset 14h-17h Video Color Key Register R/W Offset 20h-23h Reset Value 00001400h Reserved PLL2PWREN PLL2 Power-Down EnableBit Description Offset 28h-2Bh Clkdivsel Clock Divider Select Reserved Signen Signature Enable DTS Downscale Type SelectOffset 40h-43h Video Downscaler Coefficient Register R/W FLTCO4 Filter Coefficient 4. For the tap-4 filter Reserved Set to 338 AMD Geode SC3200 Processor Data Book 339 Offset 50h-53hOffset 54h-57h Enable Alpha Window Disable Alpha Window 158 340 AMD Geode SC3200 Processor Data Book 341 342 Bit Description Offset 90h-93h Offset 94h-97hALPHA3VAL Value for Alpha Window ALPHA2VAL Value for Alpha Window Reserved. Set to Genlocktouten GenLock Timeout Enable Ctgenlocken Enable Continuous GenLock FunctionReserved. Set to Offset 424h-427h 3121 Reserved 200 F4BAR2+Memory Offset VIP Configuration Registers VIP Support Registers F4BAR2F4 Index 18h, Base Address Register 2 F4BAR2 points to AMD Geode SC3200 Processor Data Book 345 Capture Store to Memory VBI Data Capture Store to Memory Video DataReserved. Read Only Current Field. Read Only 2322 Bit Description Video Data Capture Active. Read Only Run Status. Read Only3110 Reserved Start of each field Offset 14h-17h Offset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/W Jtag Mode Instruction Support Testability JtagMandatory Instruction Support Optional Instruction Support 350 General Specifications Power/Ground Connections and DecouplingElectro Static Discharge ESD Absolute Maximum Ratings VSS Symbol Parameter Min Typ Max Unit CommentsOperating Conditions Power Planes of External Interface Signals Power Plane Signal Names VCC Balls VSS BallsPower State Parameter Definitions DC Current DC Characteristics for On State Ball Capacitance and Inductance DC Characteristics for Active Idle, Sleep, and Off StatesSymbol ParameterNote Min Typ Max Unit Comments Pull-Up and Pull-Down Resistors Balls with PU/PD ResistorsVIO External PU or PD resistor DC Characteristics Symbol Description ReferenceWire 10. Buffer Types Inpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics Instrp DC Characteristics INT DC CharacteristicsInts DC Characteristics INTS1 DC Characteristics Inusb DC Characteristics ODn DC Characteristics Odpci DC Characteristics Op/n DC CharacteristicsOpci DC Characteristics Ousb DC Characteristics AC Characteristics 11. Default Levels for Measurement Switching ParametersSymbol Parameter Value CLK Inputs Memory Controller InterfaceOutputs 32581CElectrical Specifications 12. Memory Controller Timing ParametersSDCLK30, Sdclkout high time 233 MHz 266 MHz 364 T1, t2, t3 SDCLK30 Control Output, MA120BA10, MD630 MD630 Data Valid Read Data Video Port 13. Video Input Port Timing Parameters Vpckin Vref TFT Interface 14. TFT Timing Parameters Tftdck rise/fall time between 0.8VTftdck period time multiplexed on IDE Tftdck period time multiplexed on 16. ACCESS.bus Output Timing Parameters ACCESS.bus Interface15. ACCESS.bus Input Timing Parameters AB1D AB2D AB1C AB2C 370 AB1D AB2D AB1C AB2CAB1D AB2D AB1C 17. PCI AC Specifications PCI Bus Interface Equation a Equation B 16VIO64VIO 18. PCI Clock Parameters Pciclk 0.4 V IO 19. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments20. Measurement Condition Parameters Power SignalsInput Valid Ms typ Symbol Parameter Bits Type Comments Sub-ISA Interface21. Sub-ISA Timing Parameters Bus Width Min Bus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR# ROMCS#/DOCCS# IOR#/RD#/TRDE#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW# DOCCS#/ROMCS# IOCS10#IOW#/WR# MEMW#/DOCW# TRDE# D150 LPC Interface 22. LPC and Serirq Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pF IDE signals rise time from 0.1V IO to 0.9V IO = 40 pFIDE Interface 23. IDE General Timing Parameters IDERST# pulse width Mode Symbol Parameter Unit Comments 24. IDE Register Transfer to/from Device Timing ParametersCycle time min Width 8-bit min Addr valid1 IDEIOR0# IDEIOW0# Write IDEDATA70Read IDEDATA70 IDEIORDY0 2,3 25. IDE PIO Data Transfer to/from Device Timing Parameters AMD Geode SC3200 Processor Data Book 385 386 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 26. IDE Multiword DMA Data Transfer Timing Parameters 388 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC3200 Processor Data Book 389 Mode Symbol Parameter Min Max Unit Comments27. IDE UltraDMA Data Burst Timing Parameters IDEREQ0 STOP0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0 IDEIRDY0 DSTROBE0 at device IDEDATA150 at device IDEIRDY0 DSTROBE0 at hostIDEDATA150 at host AMD Geode SC3200 Processor Data Book 391 IDEDREQ0 device IDEDACK0 host IDEIOW0STOP0 hostIDEIOR0HDMARDY0 392 AMD Geode SC3200 Processor Data Book 393 IDEDREQ0 deviceIDEIOW0# STOP0# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# host IDEIRDY0 DSTROBE0 device IDEDATA150 deviceIDECS01# IDEADDR20 DevicetUI IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# host HSTROBE0# At hostIDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at device IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# host IDEIORDY0# DDMARDY0#IDEIOR0# HSTROBE0# AMD Geode SC3200 Processor Data Book 397 398 IDEIORDY0# DDMARDY0# deviceIDEDATA150 host IDEADDR20 IDECS01# AMD Geode SC3200 Processor Data Book 399 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Full Speed Receiver EOP Width Note Low Speed Source Note Source EOP width Host upstreamReceiver data jitter tolerance for paired Low Speed Receiver EOP Width Note Rise Time Fall Time Differential Data LinesDifferential Data Lines Crossover Points 2.0 Consecutive Transitions Differential Data to SE0 Skew Data Crossover LevelEOP Width Differential Crossover Points Data Lines Modulation signal period TCPN + Transmitter Sharp-IR and Consumer Remote ControlSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg register FIR Fast IR Port 30. Fast IR Port Timing ParametersMIR Busy ACK# STB# Unit Comments Symbol Parameter Min32. Enhanced Parallel Port Timing Parameters 33. ECP Forward Mode Timing Parameters Extended Capabilities Port ECPAFD# Busy 34. ECP Reverse Mode Timing Parameters BUSY# Audio Interface AC97 35. AC Reset Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delaySync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width 37. AC97 Clocks Parameters AC97CLK Vold 38. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 39. AC97 Signal Rise and Fall Timing Parameters 40. AC97 Low Power Mode Timing Parameters End of Slot 2 to Bitclk Sdatain lowSlot Bitclk Sdataout Power Management Interface Power management event to ONCTL# Assertion41. PWRBTN# Timing Parameters ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC3200 Processor Data Book 417 TDI, TMS setup time Non-test inputs setup timeJtag Interface 45. Jtag Timing Parameters TDI, TMS hold time Output Signals Input SignalsTDI TMS TDO AMD Geode SC3200 Processor Data Book 419 420 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Heatsink Considerations ExampleAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C Therefore Physical Dimensions AMD Geode SC3200 Processor Data Book 423 BGU481 Package Bottom View 424 Order Information Ordering Part Number Core FrequencyMHz Degree C Package Revision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History AMD Geode SC3200 Processor Data Book 427 89V toAppendix a Data Book Revision History 32581C