AMD SC3200 manual DMA Page Registers

32581C Core Logic Module - ISA Legacy Register Space

Table 6-43. DMA Channel Control Registers (Continued)

Bit

Description

I/O Port 0DEh	DMA Write Mask Register Command, Channels 7:4 (W)
Note: Channels 5, 6, and 7 are not supported.

			Table 6-44. DMA Page Registers
Bit		Description
I/O Port 081h			DMA Channel 2 Low Page Register (R/W)
Address bits [23:16] (byte 2).
I/O Port 082h			DMA Channel 3 Low Page Register (R/W)
Address bits [23:16] (byte 2).
I/O Port 083h			DMA Channel 1 Low Page Register (R/W)
Address bits [23:16] (byte 2).
I/O Port 087h			DMA Channel 0 Low Page Register (R/W)
Address bits [23:16] (byte 2).
I/O Port 089h			DMA Channel 6 Low Page Register (R/W)
Nor supported.
I/O Port 08Ah			DMA Channel 7 Low Page Register (R/W)
Not supported.
I/O Port 08Bh			DMA Channel 5 Low Page Register (R/W)
Not supported.
I/O Port 08Fh			ISA Refresh Low Page Register (R/W)
Refresh address.
I/O Port 481h			DMA Channel 2 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note:	This register is reset to 00h on any access to Port 081h.
I/O Port 482h			DMA Channel 3 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note:	This register is reset to 00h on any access to Port 082h.
I/O Port 483h			DMA Channel 1 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note:	This register is reset to 00h on any access to Port 083h.
I/O Port 487h			DMA Channel 0 High Page Register (R/W)
Address bits [31:24] (byte 3).
Note:	This register is reset to 00h on any access to Port 087h.
I/O Port 489h			DMA Channel 6 High Page Register (R/W)
Not supported
I/O Port 48Ah			DMA Channel 7 High Page Register (R/W)
Not spported
I/O Port 48Bh			DMA Channel 5 High Page Register (R/W)
Not supported

300 AMD Geode™ SC3200 Processor Data Book