32581C

Signal Definitions

 

 

3.4.8Low Pin Count (LPC) Bus Interface Signals

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

LAD3

L29

I/O

LPC Address-Data.Multiplexed command,

GPIO35

 

 

 

address, bidirectional data, and cycle status.

 

LAD2

L30

 

GPIO34

 

 

 

 

 

 

 

LAD1

L31

 

 

GPIO33

 

 

 

 

 

LAD0

M28

 

 

GPIO32

 

 

 

 

 

LDRQ#

L28

I

LPC DMA Request. Encoded DMA request for

GPIO36

 

 

 

LPC interface.

 

 

 

 

Note: If LDRQ# function is selected but not

 

 

 

 

used, tie LDRQ# high.

 

 

 

 

 

 

LFRAME#

K31

O

LPC Frame. A low pulse indicates the beginning

GPIO37

 

 

 

of a new LPC cycle or termination of a broken

 

 

 

 

cycle.

 

 

 

 

 

 

LPCPD#

K28

O

LPC Power-Down.Signals the LPC device to pre-

GPIO38/IRRX2

 

 

 

pare for power shut-down on the LPC interface.

 

 

 

 

 

 

SERIRQ

J31

I/O

Serial IRQ. The interrupt requests are serialized

GPIO39

 

 

 

over a single signal, where each IRQ level is deliv-

 

 

 

 

ered during a designated time slot.

 

 

 

 

Note: If SERIRQ function is selected but not

 

 

 

 

used, tie SERIRQ high.

 

 

 

 

 

 

3.4.9IDE Interface Signals

Signal Name

Ball No.

Type

Description

Mux

 

 

 

 

 

IDE_RST#

AA1

O

IDE Reset. This signal resets all the devices that are

TFTDCK

 

 

 

attached to the IDE interface.

 

 

 

 

 

 

IDE_ADDR2

U2

O

IDE Address Bits. These address bits are used to

TFTD4

 

 

 

access a register or data port in a device on the IDE bus.

 

IDE_ADDR1

AE1

 

TFTD2

 

 

 

 

 

 

 

IDE_ADDR0

AD3

 

 

TFTD3

 

 

 

 

 

IDE_DATA[15:0]

See

I/O

IDE Data Lines. IDE_DATA[15:0] transfers data to/from

The IDE interface is

 

Table 3-3

 

the IDE devices.

muxed with the TFT

 

on page

 

 

interface. See Table

 

40.

 

 

3-5 on page 45 for

 

 

 

 

details.

 

 

 

 

 

IDE_IOR0#

Y4

O

IDE I/O Read Channels 0 and 1. IDE_IOR0# is the read

TFTD10

 

 

 

signal for Channel 0 and IDE_IOR1# is the read signal

 

IDE_IOR1#

D28

O

GPIO6+DTR2#/

for Channel 1. Each signal is asserted at read accesses

 

 

 

BOUT2+SDTEST5#

 

 

 

to the corresponding IDE port addresses.

 

 

 

 

 

 

 

 

 

IDE_IOW0#

AD2

O

IDE I/O Write Channels 0 and 1. IDE_IOW0# is the

TFTD9

 

 

 

write signal for Channel 0. IDE_IOW1# is the write signal

 

IDE_IOW1#

C28

O

GPIO9+DCD2#+

for Channel 1. Each signal is asserted at write accesses

 

 

 

SDTEST2

 

 

 

to corresponding IDE port addresses.

 

 

 

 

 

 

 

 

 

IDE_CS0#

AF2

O

IDE Chip Selects 0 and 1. These signals are used to

TFTD5

 

 

 

select the command block registers in an IDE device.

 

IDE_CS1#

P2

O

TFTDE

 

 

 

 

 

 

58

AMD Geode™ SC3200 Processor Data Book

Page 58
Image 58
AMD SC3200 Low Pin Count LPC Bus Interface Signals, IDE Interface Signals, IDE I/O Write Channels 0 and 1. IDEIOW0# is