Bit Description, 242 | AMD SC3200 specification

32581CCore Logic Module - SMI Status and ACPI Registers - Function 1

		Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)
Bit	Description

21	EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 5 to 1.

20	EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 4 to 1.

19	EXT_SMI3 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 3 to 1.

18	EXT_SMI2 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 2 to 1.

17	EXT_SMI1 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 1 to 1.

16	EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 0 to 1.

15	EXT_SMI7 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI7.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 7 to 1.

14	EXT_SMI6 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 6 to 1.

13	EXT_SMI5 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 5 to 1.

12	EXT_SMI4 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 4 to 1.

11	EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.
	0:	No.
	1:	Yes.
	To enable SMI generation, set bit 3 to 1.

242	AMD Geode™ SC3200 Processor Data Book

Image 242

AMD SC3200 manual Bit Description, 242

Contents

Publication ID 32581C AMD Geode SC3200 Processor Data Book Advanced Micro Devices, Inc. All rights reserved Contacts Trademarks Contents Core Logic Module Electrical SpecificationsPackage Specifications Video Processor Module Typical Battery Current Normal Operation Mode Power Supply ConnectionsTypical Battery Configuration ACCESS.bus Data Transaction 316 Multiword DMA Data Transfer Timing Diagram 388Fast IR MIR and FIR Timing Diagram 405 360 412 410411 413 32581C Parallel Port Configuration Register Serial Ports 1 and 2 Configuration RegisterACB1 and ACB2 Configuration Register System Power States 164 Banks 0 and 1 Common Control and Status Registers 116117 165 F2BAR4+I/O Offset IDE Controller Configuration Registers Pciusb USB PCI Configuration Register SummaryF0BAR0+I/O Offset Gpio Configuration Registers F3 PCI Header Registers for Audio Configuration 387 383385 Jtag Timing Parameters 418 QJC ×C/W 421 Core Logic General DescriptionVideo Processor SuperI/O GX1 Processor Module FeaturesGeneral Features Video Processor Module SuperI/O Module Other FeaturesNand Eeprom 32581C Architecture Overview 32581C GX1 ModuleMemory Controller SC3200 Memory Controller Registers Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Register Summary MCMEMCNTRL2 R/W Rsvd Reserved. Write as 0070h Bit Description GXBASE+8408h-840BhMcbankcfg R/W Rsvd Reserved. Write as GXBASE+840Ch-840Fh Mcdracc R/W Mcgbaseadd R/WMcdradd R/W 1 GX1 Module Interface Fast-PCI BusDisplay Video Input Port Power-On Reset Clock, Timers, and Reset LogicReset Logic System Reset 32581C Interface ACCESS.busSystem Memory USB Mnemonic Definition Signal Definitions LegendBall Assignments AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball Number RD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 Signal Name Ball No BGU481 Ball Assignment Sorted Alphabetically by Signal Name32581CSignal Definitions FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options Default Alternate Ball No Signal Configuration Multiplexing ConfigurationTwo-Signal/Group Multiplexing TFT, PCI, GPIO, System Internal Test Three-Signal/Group MultiplexingACCESS.bus AC97 Fpci Monitoring AB1 Gpio Gpio PCI2TFT3 IDE2 Four-Signal/Group Multiplexing Maximum Core Clock Multiplier. These strap signals Signal DescriptionsSignal Name Ball No Type Description Mux Boot ROM is 16 Bits Wide. This strap signal enables Memory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKE Video Port Interface Signals Video Port Clock Input. The clock input from TFT Interface Signals ACCESS.bus Interface Signals Multiplexed Address and Data. a bus transaction con PCI Bus Interface SignalsMultiplexed Command and Byte Enables. During TRDY# FRAME#IRDY# STOP# BHE# LOCK#DEVSEL# SERR# VIP REQ1#REQ0# USB Sub-ISA Interface Signals IDE Chip Selects 0 and 1. These signals are used to Low Pin Count LPC Bus Interface SignalsIDE Interface Signals IDE I/O Read Channels 0 and 1. IDEIOR0# is the read Universal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals Data Terminal Ready Outputs. When low, indicate to Parallel Port Interface Signals FFRAME# Fast Infrared IR Port Interface SignalsSTB#/WRITE# IRRX1 AK8 14 AC97 Audio Interface Signals Serial Bus Synchronization. This bit is asserted to syn Suspend Power Plane Control 1 and 2. Control signal Power Management Interface SignalsGeneral Purpose Wakeup I/Os. These signals each KHz Output Clock Gpio Interface Signals Fast-PCI Bus Monitoring Signals. When enabled, this Debug Monitoring Interface SignalsJtag Interface Signals System Management Interrupt. This is the input to Memory Internal Test Signals. These signals are used Test and Measurement Interface SignalsPLL6, PLL5 and PLL2 Bypass. These signals are used Thermal Diode Positive / Negative. These signals are Power, Ground and No Connections1 General Configuration Block 32581C Configuration Block AddressesGeneral Configuration Block Register Summary Offset Width Bits Type Name Reset Value Reference PMR27 Ball # Internal Test Signals Name Add’l DependenciesOther Signal Add’l Dependencies Fpcimon Ball # IDE Signals Gpio and TFT Signals Name TFT Name Add’l Dependencies BitPP/ACB1/FPCI Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to 32581CGeneral Configuration Block Reserved Bit Description Offset 39h-3Bh Interrupt Selection Register Intsel R/W Reset Value 00hReset Value xxh Offset 3Ch Watchdog Timer Functional Description 3describes the Watchdog registers Watchdog RegistersWatchdog Interrupt Usage Hints Watchdog Status Register Wdsts R/WC Reset Value 00h High-Resolution TimerHigh-Resolution Timer Registers Offset 05h-07h Tmen Timer Interrupt Enable Reset Value xxxxxxxxhTmclksel Timer Clock Select Bit Description Offset 08h-0Bh Clock Generation Block Diagram Clock Generators and PLLs Component Parameters Values Tolerance 1 27 MHz Crystal OscillatorCrystal Oscillator Circuit Components Core Clock Frequency 2 GX1 Module Core ClockInternal Fast-PCI Clock Strapped Core Clock Frequency Video Processor Clocks SuperI/O ClocksCore Logic Module Clocks 8describes the registers of the clock generator and PLL Clock Generator ConfigurationClock Registers 1514 AB1C AB1D AB2C AB2D Outstanding FeaturesISA Serial Port 3 / Infrared IR Communication Port PC98 and Acpi CompliantSerial Port System Wakeup Control SWC Module Architecture AccessInternal Internal Signals Index-Data Register Pair Configuration Structure / AccessSIO Configuration Options LDN Assignments Default Configuration Setup Address Decoding Logical Device Control and Configuration Registers Standard Configuration RegistersSIO Control and Configuration Registers Standard Logical Device Configuration Registers Standard Configuration Registers DMA Channel Select 1 R/W Index F0h-FEh Logical Device Configuration R/W32581CSuperI/O Module Index Type Name Power Rail Reset Value SIO Control and Configuration RegistersSIO Control and Configuration Register Map SID. SIO ID Logical Device Control and Configuration Relevant RTC Configuration Registers RTC Configuration Registers Base Address MSB register Relevant SWC RegistersLDN 01h System Wakeup Control 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers 11. Relevant Serial Ports 1 and 2 Registers 12. Serial Ports 1 and 2 Configuration RegisterSerial Ports 1 and 2 Configuration register LDN 03h and 08h Serial Ports 1 ACB1 and ACB2 Configuration register 14. ACB1 and ACB2 Configuration RegisterLDN 05h and 06h ACCESS.bus Ports 1 13. Relevant ACB1 and ACB2 Registers 16. Parallel Port Configuration Register 15. Relevant Parallel Port Registers Bus Interface X32I External X32O Battery = 0.1 μFReal-Time Clock RTC RTC Clock Generation Oscillator Startup Signal ParametersExternal Elements External Oscillator Daylight Saving AlarmsTimekeeping Data Format Leap Years BT1 Power SupplyRTC 18. System Power States 108 Battery-Backed RAMs and RegistersInterrupt Handling 20. RTC Registers RTC Registers19. RTC Register Map Index Type Name 110 Index 05h Hours Alarm Register Hora R/WIndex 04h Hours Register HOR R/W Index Programmable Century Register CEN R/W Index Programmable Month Alarm Register Mona R/WIndex 0Ch RTC Control Register C CRC RO AMD Geode SC3200 Processor Data Book 111 23. BCD and Binary Formats 21. Divider Chain Control / Test Selection22. Periodic Interrupt Rate Encoding Rate Select Periodic Interrupt Divider Rate ms Chain Output RTC General-Purpose RAM Map 24. Standard RAM Map 0Eh 7Fh Battery-backed general-purpose Byte RAM00h 7Fh Battery-backed general-purpose Byte RAM 25. Extended RAM Map 26. Time Range Limits for Ceir Protocols System Wakeup Control SWCEvent Detection Type Name Value SWC Registers27. Banks 0 and 1 Common Control and Status Register Map Offset Type Name Value 29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Ceir Pulse Change, Range 1, High Limit Bit Description Ceir Wakeup Range 1 RegistersBank 1, Offset 0Ah IRWTR1L Register R/W Ceir Wakeup Range 2 Registers ABD ABC ACCESS.bus InterfaceData Transactions AMD Geode SC3200 Processor Data Book 119 ABC ACK Acknowledge ACK CycleABD MSB Arbitration on the Bus Master ModeAcknowledge After Every Byte Rule Addressing Transfer Formats Master Receive Sending the Address ByteMaster Transmit Master Stop Slave Mode Configuration 32. ACB Registers ACB Registers31. ACB Register Map MASTER. RO EN Enable Reserved Inten Interrupt EnableSaen Slave Address Enable Stop Stop 33. Parallel Port Register Map for First Level Offset Legacy Functional BlocksParallel Port 34. Parallel Port Register Map for Second Level Offset Bits 35. Parallel Port Bit Map for First Level Offset36. Parallel Port Bit Map for Second Level Offset 128 Uart Functionality SP1 and SP2 Type Name 40. Bank 2 Register Map 38. Bank Selection Encoding39. Bank 1 Register Map 41. Bank 3 Register Map Register Bits 42. Bank 0 Bit Map43. Bank 1 Bit Map Register Bits Offset 132 44. Bank 2 Bit Map45. Bank 3 Bit Map IRCP/SP3 Register and Bit Maps 3.1 IR/SP3 Mode Register Bank Overview46. Bank 0 Register Map 01h Register Throughout Offset 00h All Banks 49. Bank 2 Register Map 47. Bank Selection Encoding48. Bank 1 Register Map BSR Bits Bank Selected Functionality 52. Bank 5 Register Map 50. Bank 3 Register Map51. Bank 4 Register Map 55. Bank 0 Bit Map 53. Bank 6 Register Map54. Bank 7 Register Map 58. Bank 3 Bit Map 56. Bank 1 Bit Map57. Bank 2 Bit Map 59. Bank 4 Bit Map 62. Bank 7 Bit Map 60. Bank 5 Bit Map61. Bank 6 Bit Map Feature List Video Processor Interface ConfigIntegrated Audio Low Pin Count LPC Interface Fast-PCI Interface to External PCI Bus Pserial Interface IDE Controller IDE Configuration RegistersPIO Mode Video Retrace Interrupt Physical Region Descriptor Format Stop UltraDMA/33 Signal DefinitionsUltraDMA/33 Mode DMARDY# Strobe Ideiordy IOCS0#/IOCS1# Universal Serial BusSub-ISA Bus Interface Docw 146 Sub-ISA Support of Delayed PCI TransactionsSub-ISA Bus Cycles FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# 5.4 I/O Recovery DelaysREQ# GNT# Sub-ISA Bus Data Steering ISA DMA 148 ROM Interface PCI and Sub-ISA Signal Cycle MultiplexingCycle Multiplexed PCI / Sub-ISA Balls PCI DMA Controller FRAME# TRDY#, IRDY#ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP# DMA Channels DMA Transfer Types DMA Transfer ModesDMA Controller Registers DMA Priority DMA Page Registers and Extended Addressing Programmable Interval TimerDMA Addressing Capability DMA Address Generation Master PIC Interrupt MappingProgrammable Interrupt Controller Mapping PIC Shadow Register PIC Interrupt SequencePIC I/O Registers PCI Compatible Interrupts 7.1 I/O Port 092h System Control Fast Keyboard Gate Address 20 and CPU ResetKeyboard Support 7.2 I/O Port 061h System Control Power Management Logic Wakeup Events Capability Power Management Events Power Planes Control Signals vs Sleep StatesPower Planes vs. Sleep/Global States Thermal Monitoring Power ButtonPower Button Override AMD Geode SC3200 Processor Data Book 159 APM Support Power Management ProgrammingCPU Power Management Suspend Modulation AMD Geode SC3200 Processor Data Book 161 Volt SuspendSave-to-Disk General Purpose Timers Peripheral Power ManagementDevice Idle Timers and Traps Acpi Timer Register F1BAR0+I/O Power Management SMI Status Reporting RegistersModule Located at F0 Index xxh Unless Otherwise Noted Device Power Management Programming SummaryPower Management Programming Summary F1BAR0+I/O Gpio Interface Integrated Audio Audio Data Buffer 11. Physical Region Descriptor FormatByte Size PRD1 PRD2 PRD3 12.2 AC97 Codec Interface Codec Configuration/Control RegistersCodec Command Register Codec Gpio Status and Control Registers VSA Technology Trap SMI Enable RegisterVSA Technology Support Hardware Audio SMI Related Registers Module Core Logic Module Internal IRQ Control Register IRQ Configuration RegistersInternal IRQ Enable Register LPC Interface 12. Cycle Types Register Descriptions PCI Configuration Space and Access Methods13. PCI Configuration Address Register 0CF8h Mats are found Ter’s reset values and page references where the bit forRegister Summary AMD Geode SC3200 Processor Data Book 175 Width Reset Reference F0 Index BitsCore Logic Module Register Summary 32581C 32581CCore Logic Module Register Summary 176 F0BAR0+ 15. F0BAR0 Gpio Support Registers Summary16. F0BAR1 LPC Support Registers Summary F0BAR1+ 18. F1BAR0 SMI Status Registers Summary F1BAR0+ AMD Geode SC3200 Processor Data Book 179 19. F1BAR1 Acpi Support Registers SummaryF1BAR1+ Width Reset Reference F2 Index Bits 180 22. F3 PCI Header Registers for Audio Support Summary Width Reset Reference F3 Index Bits21. F2BAR4 IDE Controller Support Registers Summary F2BAR4+ F3BAR0+ Width Reset23. F3BAR0 Audio Support Registers Summary 182 F5BAR0+ Width Reset Reference F5 Index Bits25. F5BAR0 I/O Control Support Registers Summary AMD Geode SC3200 Processor Data Book 183 Pciusb 26. Pciusb USB PCI Configuration Register SummaryName Reset Value Width Reference Index Bits AMD Geode SC3200 Processor Data Book 185 27. Usbbar USB Controller Registers SummaryUSBBAR0 186 28. ISA Legacy I/O Register SummaryDMA Page Registers Table Programmable Interrupt Controller Registers Table Programmable Interval Timer Registers TablePort Type Name Reference Keyboard Controller Registers Table General Remarks Chipset Register SpaceBridge, GPIO, and LPC Registers Function AMD Geode SC3200 Processor Data Book 189 Index 06h-07h PCI Status Register R/WData Parity Detected. This bit is set when Index 09h-0Bh Index 0Eh PCI Header Type RO Reset Value 80hBit Description Index 08h Index 0Ch PCI Subtractive Decode AMD Geode SC3200 Processor Data Book 191 Index 43h Reset Control Register R/W Reset Value 01hIndex 42h 192 Index 47h Index 45hIndex 46h AMD Geode SC3200 Processor Data Book 193 PIT Software Reset Reset Value FFFFFFFFhReset Value 7Bh PIT Counter 1 Enable AMD Geode SC3200 Processor Data Book 195 ROM/AT Logic Control Register R/W Reset Value 98hGenerate SMI on A20M# Toggle Index 5Bh Decode Control Register 2 R/W Bit Description Index 54h-59hIndex 5Ah 196 INTD# Ball AA2 Target Interrupt INTB# Ball C26 Target InterruptINTA# Ball D26 Target Interrupt INTC# Ball C9 Target Interrupt 198 Index 73h Index 72hChip Select 1 Positive Decode IOCS1# Index 76h DiskOnChip Chip Select Positive Decode DOCCS# Index 7Ch-7Fh DOCCS# Control Register R/W3127 200 Index 81h Power Management Enable Register 2 R/W AMD Geode SC3200 Processor Data Book 201 202 Parallel/Serial Access Trap Power Management Enable Register 3 R/W Reset Value 00hKeyboard/Mouse Access Trap AMD Geode SC3200 Processor Data Book 203 Index 83h Power Management Enable Register 4 R/W Floppy Disk Access TrapPrimary Hard Disk Access Trap 204 Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC3200 Processor Data Book 205 206 AMD Geode SC3200 Processor Data Book 207 Index 88h General Purpose Timer 1 Count Register R/W 208 Re-trigger General Purpose Timer 1 on Floppy Disk Activity AMD Geode SC3200 Processor Data Book 209 210 Index 8Bh General Purpose Timer 2 Control Register R/WIndex 8Dh Video Speedup Timer Count Register R/W AMD Geode SC3200 Processor Data Book 211 Index 8Fh-92hIndex 93h Index 98h-99h Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/WIndex 97h 212 Index A6h-A7h Video Idle Timer Count Register R/W Index A8h-A9h Video Overflow Count Register R/W Index B0h-B3h Index AEh CPU Suspend Command Register WOIndex AFh Suspend Notebook Command Register WO Index B4h AMD Geode SC3200 Processor Data Book 215 Index B9h PIC Shadow Register ROIndex BAh PIT Shadow Register RO Index BDh-BFh Index BCh Clock Stop Control Register R/W Reset Value 00hReserved. Set to CPU Clock Stop Index C0h-C3h Index CDh Bit Description Index CChMask Index CEh Index F5h Second Level PME/SMI Status Register 2 RC Index EDh-F3hIndex F4h 218 Index F6h Second Level PME/SMI Status Register 3 RC AMD Geode SC3200 Processor Data Book 219 Index F7h Second Level PME/SMI Status Register 4 RC 220 Index F8h-FFh Gpio Support Registers 30. F0BAR0+I/O Offset Gpio Configuration RegistersI/O mapped registers accessed through F0BAR0 Ration registers are located. -29gives the bit formats AMD Geode SC3200 Processor Data Book 223 Offset 14h-17h GPDI1 Gpio Data In 1 Register ROF0BAR0+I/O Offset 18h is set, this edge generates a PME Bank 224 AMD Geode SC3200 Processor Data Book 225 3121 31. F0BAR1+I/O Offset LPC Interface Configuration RegistersLPC Support Registers Reserved. Set to AMD Geode SC3200 Processor Data Book 227 228 Number of IRQ Data Frames Reserved Serial IRQ EnableSerial IRQ Interface Mode AMD Geode SC3200 Processor Data Book 229 230 LPC Floppy Disk Controller Address Select. Selects I/O Port LPC Game Port 1 Address Select. Selects I/O PortLPC Game Port 0 Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port 232 Bit SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi Support AMD Geode SC3200 Processor Data Book 235 33. F1BAR0+I/O Offset SMI Status RegistersSMI Status Support Registers 236 Suspend Modulation Enable Mirror. Read to ClearOffset 02h-03h Top Level PME/SMI Status Register RO/RC AMD Geode SC3200 Processor Data Book 237 Offset 04h-05h 238 AMD Geode SC3200 Processor Data Book 239 240 Offset 0Ah-1BhThese addresses should not be written Offset 1Ch-1Fh AMD Geode SC3200 Processor Data Book 241 Offset 24h-27h External SMI Register R/W3124 242 AMD Geode SC3200 Processor Data Book 243 244 Offset 28h-4Fh Not Used Reset Value 00h50h-FFh Acpi Support Registers Offset 06h Smicmd OS/BIOS Requests Register R/W34. F1BAR1+I/O Offset Acpi Support Registers Clkval Clock Throttling Value. CPU duty cycle 1412 246 Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W1511 AMD Geode SC3200 Processor Data Book 247 248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 252 Gpwio Control Register 1 R/W Reset Value 00hGpwio Control Register 2 R/W Reset Value 00h Reserved 3117 Reserved Gpwio Data Register R/W Reset Value 00hOffset 17h AMD Geode SC3200 Processor Data Book 253 Offset 21h-FFh 254 IDE Controller Registers Function 256 PIOMODE. PIO modeBit Description Index 30h-3Fh 3024 Reset Value 00009172hReset Value 00077771h AMD Geode SC3200 Processor Data Book 257 Index 60h-FFh Bit Description Index 50h-53hIndex 58h-5Bh 258 IDE Controller Support Registers AMD Geode SC3200 Processor Data Book 259 Offset 0Bh Offset 09hOffset 0Ah Offset 0Ch-0Fh 37. F3 PCI Header Registers for Audio Configuration Audio Registers Function 2921 38. F3BAR0+Memory Offset Audio Configuration RegistersAudio Support Registers Offset 04h-07h AMD Geode SC3200 Processor Data Book 263 264 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC AMD Geode SC3200 Processor Data Book 265 266 Reserved. Must be set to Mask Internal IRQ14. Write Only 32581CCore Logic Module Audio Registers FunctionMask Internal IRQ15. Write Only Mask Internal IRQ11. Write Only Assert Masked Internal IRQ14 Mask Internal IRQ4. Write OnlyMask Internal IRQ3. Write Only Reserved. Set to Assert Masked Internal IRQ12 Bit Description Assert Masked Internal IRQ1 270 Offset 2Ah-2Bh Audio Bus Master 1 Command Register R/W Reset Value 00hOffset 29h Audio Bus Master 1 SMI Status Register RC Offset 2Ch-2Fh Offset 32h-33h Audio Bus Master 2 Command Register R/W Reset Value 00hOffset 31h Audio Bus Master 2 SMI Status Register RC Offset 34h-37h Offset 3Ah-3Bh Audio Bus Master 3 Command Register R/W Reset Value 00hOffset 39h Audio Bus Master 3 SMI Status Register RC Offset 3Ch-3Fh Offset 42h-43h Audio Bus Master 4 Command Register R/W Reset Value 00hOffset 41h Audio Bus Master 4 SMI Status Register RC Offset 44h-47h Offset 4Ah-4Bh Audio Bus Master 5 Command Register R/W Reset Value 00hOffset 49h Audio Bus Master 5 SMI Status Register RC Offset 4Ch-4Fh Bus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus Expansion Index 20h-23h Core Logic Module X-Bus Expansion Interface Function 32581CBit Description Index 1Ch-1Fh Index 24h-27h Index 50h-53h F5BAR4 Mask Address Register R/W Index 48h-4Bh F5BAR2 Mask Address Register R/WIndex 4Ch-4Fh F5BAR3 Mask Address Register R/W Index 54h-57h F5BAR5 Mask Address Register R/W Bit Description Index 64h-67h AMD Geode SC3200 Processor Data Book 279 Bus Expansion Support Registers Base address that allows PCI access to additional I/O Con40. F5BAR0+I/O Offset X-Bus Expansion Registers F5 Index 10h, Base Address Register 0 F5BAR0 set AMD Geode SC3200 Processor Data Book 281 Iotestporten Debug Test Port EnableIostrapidselselect Idsel Strap Override Bit Description 41. Pciusb USB PCI Configuration RegistersUSB Controller Registers Pciusb 282 Core Logic Module USB Controller Registers Pciusb 32581C Reset Value 08hIndex 0Dh Latency Timer Register R/W Index 06h-07h Status Register R/W Reset Value 50h Reset Value 0E11hReset Value A0F8h Index 30h-3Bh 42. USBBAR+Memory Offset USB Controller Registers AMD Geode SC3200 Processor Data Book 285 RootHubStatusChangeEnable HcInterruptEnable Register R/W Reset Value = 00000000hOwnershipChangeEnable FrameNumberOverflowEnable Offset 28h-2Bh 287 Bit Description Offset 34h-37h Reset Value = 00000628hReset Value = 01000003h Offset 38h-3Bh 3018 Read LocalPowerStatusChange. Not supported. Always readOffset 50h-53h HcRhStatus Register R/W AMD Geode SC3200 Processor Data Book 289 Read PortSuspendStatus HcRhPortStatus1 Register R/W Reset Value = 00000000hRead PortResetStatus 290 AMD Geode SC3200 Processor Data Book 1510 Bit Description Read PortEnableStatusRead CurrentConnectStatus AMD Geode SC3200 Processor Data Book 291 292 Offset 100h-103h Reset Value = xxhOffset 60h-9Fh 319 Reserved. Read/Write 0s 318 Reserved. Read/Write 0s Reset Value = 000000xxhOffset 104h-107h 294 ISA Legacy Register Space 43. DMA Channel Control Registers 32581CCore Logic Module ISA Legacy Register Space Priority ModeTiming Mode Write Bit Description Port 00Bh Transfer ModeChannel Number Mode Select Address Direction 298 Write DMA Command Register, ChannelsUndefined Port 0D6h Bit Description Port 0D2hPort 0D4h Port 0D8h 44. DMA Page Registers 45. Programmable Interval Timer Registers Counter Value Read Current Counter Mode BCD ModeBit Description Port 042h Write Port 043h R/W 46. Programmable Interrupt Controller Registers Bit Description IRQ2 / IRQ10 Mask Poll CommandRegister Read Mode IRQ1 / IRQ9 Mask IRQ5 / IRQ13 In-Service Interrupt Service Register IRQ7 / IRQ15 In-ServiceIRQ6 / IRQ14 In-Service IRQ4 / IRQ12 In-Service 47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers 308 Hardware Video Acceleration General FeaturesVideo Input Port VIP Graphics-Video Overlay and Blending VIP Mixer/Blender VBI Support Functional DescriptionVideo Support AMD Geode SC3200 Processor Data Book 311 Active Video GenLock Direct Video ModeVideo Input Port VIP Program the VIP bus master address registers Capture Video ModeBob Program other VIP bus master support registers Weave AMD Geode SC3200 Processor Data Book 315 316 Field Interrupt Capture VBI ModePing-pongs between the two buffers during runtime Line Buffer Video BlockVideo Input Formatter AMD Geode SC3200 Processor Data Book 317 Horizontal Downscaler Horizontal Downscaler with 4-Tap FilteringFiltering 2.5 2-Tap Vertical and Horizontal Upscalers Line BuffersFormatter AMD Geode SC3200 Processor Data Book 319 RAM Mixer/Blender BlockRGB YUV Gamma Correction Valid Mixing/Blending ConfigurationsYUV to RGB CSC in Video Data Path Color/Chroma Key Video Window Color/Chroma Key and Mixer/BlenderGraphics Window Cursor Window Color Truth Table for Alpha BlendingMixing/Blending Operation CHROMASEL1 12. Color Key and Alpha Blending Logic 324 HSYNC, VSYNC, TFTDE, Tftdck Power SequenceTFT Interface T1 is a programmable multiple of frame time T0+T1 Integrated PLL 326 F4BAR0+ F4BAR0 Video Processor Configuration Registers SummaryF4 PCI Header Registers for Video Processor Support Summary 32581CVideo Processor Module Register Summary 328 AMD Geode SC3200 Processor Data Book 329 F4BAR2 VIP Support Registers SummaryF4BAR2+ Video Processor Registers Function Reset Value 0504hReset Value 030000h 3112 VIP Base Address 110 Address Range. Read Only Index 3Eh-FFh Reserved AMD Geode SC3200 Processor Data Book 331 Video Processor Support Registers F4BAR0 Video Configuration Register R/W Reset Value 00000000hEN42X Enable 42x Format. Allows format selection To 0 or 1 should be written with a value that is read AMD Geode SC3200 Processor Data Book 333 Offset 04h-07h Display Configuration Register R/WReserved. Write as read Reserved Bit Description Offset 08h-0Bh Video X Position Register R/W 334 Bit Description Offset 14h-17h Video Color Key Register R/W Offset 20h-23h Bit Description Offset 28h-2Bh Reset Value 00001400hReserved PLL2PWREN PLL2 Power-Down Enable Clkdivsel Clock Divider Select Offset 40h-43h Video Downscaler Coefficient Register R/W Reserved Signen Signature EnableDTS Downscale Type Select FLTCO4 Filter Coefficient 4. For the tap-4 filter Reserved Set to 338 AMD Geode SC3200 Processor Data Book 339 Offset 50h-53hOffset 54h-57h Enable Alpha Window Disable Alpha Window 158 340 AMD Geode SC3200 Processor Data Book 341 342 ALPHA3VAL Value for Alpha Window Bit Description Offset 90h-93hOffset 94h-97h ALPHA2VAL Value for Alpha Window Reserved. Set to Offset 424h-427h Reserved. Set to Genlocktouten GenLock Timeout EnableCtgenlocken Enable Continuous GenLock Function 3121 Reserved 200 F4 Index 18h, Base Address Register 2 F4BAR2 points to F4BAR2+Memory Offset VIP Configuration RegistersVIP Support Registers F4BAR2 AMD Geode SC3200 Processor Data Book 345 Reserved. Read Only Current Field. Read Only Capture Store to Memory VBI DataCapture Store to Memory Video Data 2322 3110 Reserved Bit Description Video Data Capture Active. Read OnlyRun Status. Read Only Start of each field Offset 14h-17h Offset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/W Mandatory Instruction Support Jtag Mode Instruction SupportTestability Jtag Optional Instruction Support 350 Electro Static Discharge ESD General SpecificationsPower/Ground Connections and Decoupling Absolute Maximum Ratings VSS Symbol Parameter Min Typ Max Unit CommentsOperating Conditions Power State Parameter Definitions Power Planes of External Interface SignalsPower Plane Signal Names VCC Balls VSS Balls DC Current DC Characteristics for On State Ball Capacitance and Inductance DC Characteristics for Active Idle, Sleep, and Off StatesSymbol ParameterNote Min Typ Max Unit Comments VIO Pull-Up and Pull-Down ResistorsBalls with PU/PD Resistors External PU or PD resistor Wire DC CharacteristicsSymbol Description Reference 10. Buffer Types Inpci DC Characteristics Inab DC CharacteristicsInbtn DC Characteristics Ints DC Characteristics Instrp DC CharacteristicsINT DC Characteristics INTS1 DC Characteristics Inusb DC Characteristics ODn DC Characteristics Opci DC Characteristics Odpci DC CharacteristicsOp/n DC Characteristics Ousb DC Characteristics Symbol Parameter Value AC Characteristics11. Default Levels for Measurement Switching Parameters CLK Inputs Memory Controller InterfaceOutputs SDCLK30, Sdclkout high time 233 MHz 266 MHz 32581CElectrical Specifications12. Memory Controller Timing Parameters 364 BA10, MD630 T1, t2, t3SDCLK30 Control Output, MA120 MD630 Data Valid Read Data Video Port 13. Video Input Port Timing Parameters Vpckin Vref Tftdck period time multiplexed on IDE TFT Interface 14. TFT Timing ParametersTftdck rise/fall time between 0.8V Tftdck period time multiplexed on 16. ACCESS.bus Output Timing Parameters ACCESS.bus Interface15. ACCESS.bus Input Timing Parameters AB1D AB2D AB1C AB2C 370 AB1D AB2D AB1C AB2CAB1D AB2D AB1C 17. PCI AC Specifications PCI Bus Interface Equation a Equation B 16VIO64VIO 18. PCI Clock Parameters Pciclk 0.4 V IO 19. PCI Timing Parameters Measurement and Test Conditions Symbol Value Unit Comments20. Measurement Condition Parameters Input Valid PowerSignals Ms typ 21. Sub-ISA Timing Parameters Symbol Parameter Bits Type CommentsSub-ISA Interface Bus Width Min Bus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR# MEMR#/DOCR# ROMCS#/DOCCS#IOR#/RD#/TRDE# IOW#/WR# MEMW#/DOCW# IOW#/WR# MEMW#/DOCW# TRDE# DOCCS#/ROMCS#IOCS10# D150 LPC Interface 22. LPC and Serirq Timing Parameters IDE Interface 23. IDE General Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pFIDE signals rise time from 0.1V IO to 0.9V IO = 40 pF IDERST# pulse width Cycle time min Mode Symbol Parameter Unit Comments24. IDE Register Transfer to/from Device Timing Parameters Width 8-bit min Read IDEDATA70 Addr valid1IDEIOR0# IDEIOW0# Write IDEDATA70 IDEIORDY0 2,3 25. IDE PIO Data Transfer to/from Device Timing Parameters AMD Geode SC3200 Processor Data Book 385 386 IDEIOR0# IDEIOW0# Write IDEDATA150Read IDEDATA150 26. IDE Multiword DMA Data Transfer Timing Parameters 388 IDECS10#IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# AMD Geode SC3200 Processor Data Book 389 Mode Symbol Parameter Min Max Unit Comments27. IDE UltraDMA Data Burst Timing Parameters IDEIOR0# HDMARDY0# IDEREQ0STOP0 IDEIRDY0 DSTROBE0 IDEDATA150 at host IDEIRDY0 DSTROBE0 at deviceIDEDATA150 at device IDEIRDY0 DSTROBE0 at host AMD Geode SC3200 Processor Data Book 391 IDEIOR0HDMARDY0 IDEDREQ0 device IDEDACK0 hostIDEIOW0STOP0 host 392 AMD Geode SC3200 Processor Data Book 393 IDEDREQ0 deviceIDEIOW0# STOP0# IDECS01# IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# hostIDEIRDY0 DSTROBE0 device IDEDATA150 device IDEADDR20 IDEIORDY0 DDMARDY0 device DevicetUI IDEDACK0# hostIDEIOW0# STOP0# host IDEIOR0# HSTROBE0# host IDEDATA150 At host IDEIOR0# HSTROBE0# at device HSTROBE0#At host IDEDATA150 at device IDEIOR0# HSTROBE0# IDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0# DDMARDY0# AMD Geode SC3200 Processor Data Book 397 398 IDEIORDY0# DDMARDY0# deviceIDEDATA150 host IDEADDR20 IDECS01# AMD Geode SC3200 Processor Data Book 399 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostIDEDATA150 host IDECS01# IDEADDR20 Full Speed Receiver EOP Width Note Low Speed Source Note Receiver data jitter tolerance for paired Source EOP widthHost upstream Low Speed Receiver EOP Width Note Differential Data Lines Crossover Points 2.0 Rise Time Fall TimeDifferential Data Lines Consecutive Transitions EOP Width Differential Data to SE0 SkewData Crossover Level Differential Crossover Points Data Lines SIR signal pulse width Modulation signal periodTCPN + Transmitter Sharp-IR and Consumer Remote Control Setting of the Rxhsc bit bit 5 of the Rccfg register FIR Fast IR Port 30. Fast IR Port Timing ParametersMIR Busy ACK# STB# Unit Comments Symbol Parameter Min32. Enhanced Parallel Port Timing Parameters AFD# 33. ECP Forward Mode Timing ParametersExtended Capabilities Port ECP Busy 34. ECP Reverse Mode Timing Parameters BUSY# Sync inactive to Bitclk startup 162.8 Delay Audio Interface AC97 35. AC Reset Timing ParametersAC97RST# inactive to Bitclk 162.8 Startup delay AC97RST# active low pulse width 37. AC97 Clocks Parameters AC97CLK Vold 38. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN2 39. AC97 Signal Rise and Fall Timing Parameters Slot 40. AC97 Low Power Mode Timing ParametersEnd of Slot 2 to Bitclk Sdatain low Bitclk Sdataout 41. PWRBTN# Timing Parameters Power Management InterfacePower management event to ONCTL# Assertion ONCTL# PWRBTN# PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC3200 Processor Data Book 417 Jtag Interface 45. Jtag Timing Parameters TDI, TMS setup timeNon-test inputs setup time TDI, TMS hold time TDI TMS TDO Output SignalsInput Signals AMD Geode SC3200 Processor Data Book 419 420 Case-to-Ambient Thermal Resistance Example @ 85C Thermal CharacteristicsΘJC ×C/W Assume P max = 5W and TA max = 40C Therefore Heatsink ConsiderationsExample Assume P max = 9W and TA max = 40C Therefore Physical Dimensions AMD Geode SC3200 Processor Data Book 423 BGU481 Package Bottom View 424 MHz Order InformationOrdering Part Number Core Frequency Degree C Package Revision # Revisions / Comments Data Book Revision HistoryTable A-1. Revision History AMD Geode SC3200 Processor Data Book 427 89V toAppendix a Data Book Revision History 32581C