Manuals / AMD / Computer Equipment / Computer Hardware

AMD SC3200 manual 40. F5BAR0+I/O Offset X-Bus Expansion Registers, Bus Expansion Support Registers

Models: SC3200

1 428

Page 280

32581C	Core Logic Module - X-Bus Expansion Interface - Function 5

6.4.5.1 X-Bus Expansion Support Registers
F5 Index 10h, Base Address Register 0 (F5BAR0) set the	trol support registers. Table 6-40shows the support regis-
base address that allows PCI access to additional I/O Con-	ters accessed through F5BAR0.

Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers

Bit	Description

Offset 00h-03h		I/O Control Register 1 (R/W)	Reset Value: 010C0007h

31:28	Reserved.

27	IO_ENABLE_SIO_IR (Enable Integrated SIO Infrared).
	0:	Disable.
	1:	Enable.

26:25	IO_SIOCFG_IN (Integrated SIO Input Configuration). These two bits can be used to disable the integrated SIO totally or
	limit/control the base address.
	00: Integrated SIO disable.
	01: Integrated SIO configuration access disable.
	10: Integrated SIO base address 02Eh/02Fh enable.
	11: Integrated SIO base address 015Ch/015Dh enable.

24	IO_ENABLE_SIO_DRIVING_ISA_BUS (Enable Integrated SIO ISA Bus Control). Allow the integrated SIO to drive the
	internal ISA bus.
	0:	Disable.
	1:	Enable. (Default)

23:21	Reserved. Set to 0.

20	IO_USB_SMI_PWM_EN (USB Internal SMI). Route USB-generated SMI to SMI Status Register in F1BAR0+I/O Offset
	00h/02h[14].
	0:	Disable.
	1:	Enable.

19	IO_USB_SMI_EN (USB SMI Configuration). Allow USB-generated SMIs.
	0:	Disable
	1:	Enable.
	If bits 19 and 20 are enabled, the SMI generated by the USB is reported via the Top Level SMI status register at F1BAR0+I/
	O Offset 00h/02h[14].
	If only bit 19 is enabled, the USB can generate an SMI but there is no status reporting.

18	IO_USB_PCI_EN (USB). Enables USB ports.
	0:	Disable.
	1:	Enable.

17:0	Reserved.

280	AMD Geode™ SC3200 Processor Data Book

Page 280

Image 280

AMD SC3200 manual 40. F5BAR0+I/O Offset X-Bus Expansion Registers, Bus Expansion Support Registers

Contents

Publication ID 32581C AMD Geode SC3200 Processor Data BookAdvanced Micro Devices, Inc. All rights reserved Contacts TrademarksContents Electrical Specifications Package SpecificationsCore Logic Module Video Processor ModulePower Supply Connections Typical Battery ConfigurationTypical Battery Current Normal Operation Mode ACCESS.bus Data TransactionMultiword DMA Data Transfer Timing Diagram 388 Fast IR MIR and FIR Timing Diagram 405316 360410 411412 41332581C Serial Ports 1 and 2 Configuration Register ACB1 and ACB2 Configuration RegisterParallel Port Configuration Register System Power StatesBanks 0 and 1 Common Control and Status Registers 116 117164 165Pciusb USB PCI Configuration Register Summary F0BAR0+I/O Offset Gpio Configuration RegistersF2BAR4+I/O Offset IDE Controller Configuration Registers F3 PCI Header Registers for Audio Configuration383 385387 Jtag Timing Parameters 418 QJC ×C/W 421General Description Video ProcessorCore Logic SuperI/OFeatures General FeaturesGX1 Processor Module Video Processor ModuleNand Eeprom Other FeaturesSuperI/O Module 32581C Memory Controller GX1 ModuleArchitecture Overview 32581C SC3200 Memory Controller Register Summary Width Memory Offset Bits Type Name/Function Reset ValueSC3200 Memory Controller Registers MCMEMCNTRL2 R/W Bit Description GXBASE+8408h-840Bh Mcbankcfg R/WRsvd Reserved. Write as 0070h Rsvd Reserved. Write as GXBASE+840Ch-840FhMcdradd R/W Mcgbaseadd R/WMcdracc R/W Fast-PCI Bus Display1 GX1 Module Interface Video Input PortClock, Timers, and Reset Logic Reset LogicPower-On Reset System Reset32581C ACCESS.bus SystemInterface MemoryUSB Ball Assignments Signal Definitions LegendMnemonic Definition AMD Geode Configuration BGU481 Ball Assignment Sorted by Ball NumberRD# Slct Buffer1 Power Signal Name STOP# Inpci GPIO35 Inpci PWR AD0 Inpci SDCLK1 AF1 IRQ14 SDCLK0 MA7 32581CSignal Definitions BGU481 Ball Assignment Sorted Alphabetically by Signal NameSignal Name Ball No FSTOP# PD4 Vpckin Strap Options Nominal External PU/PD Strap SettingsStrap Options Multiplexing Configuration Two-Signal/Group MultiplexingDefault Alternate Ball No Signal Configuration TFT, PCI, GPIO, SystemThree-Signal/Group Multiplexing ACCESS.busInternal Test AC97 Fpci MonitoringGpio PCI2 TFT3AB1 Gpio IDE2Four-Signal/Group Multiplexing Signal Descriptions Signal Name Ball No Type Description MuxMaximum Core Clock Multiplier. These strap signals Boot ROM is 16 Bits Wide. This strap signal enablesMemory Interface Signals Column Address Strobe. RAS#, CAS#, WE# and CKEVideo Port Interface Signals Video Port Clock Input. The clock input fromTFT Interface Signals ACCESS.bus Interface SignalsMultiplexed Command and Byte Enables. During PCI Bus Interface SignalsMultiplexed Address and Data. a bus transaction con FRAME# IRDY#TRDY# STOP#LOCK# DEVSEL#BHE# SERR#REQ1# REQ0#VIP USBSub-ISA Interface Signals Low Pin Count LPC Bus Interface Signals IDE Interface SignalsIDE Chip Selects 0 and 1. These signals are used to IDE I/O Read Channels 0 and 1. IDEIOR0# is the readUniversal Serial Bus USB Interface Signals Serial Ports UARTs Interface Signals Data Terminal Ready Outputs. When low, indicate toParallel Port Interface Signals Fast Infrared IR Port Interface Signals STB#/WRITE#FFRAME# IRRX1 AK814 AC97 Audio Interface Signals Serial Bus Synchronization. This bit is asserted to synPower Management Interface Signals General Purpose Wakeup I/Os. These signals eachSuspend Power Plane Control 1 and 2. Control signal KHz Output ClockGpio Interface Signals Debug Monitoring Interface Signals Jtag Interface SignalsFast-PCI Bus Monitoring Signals. When enabled, this System Management Interrupt. This is the input toTest and Measurement Interface Signals PLL6, PLL5 and PLL2 Bypass. These signals are usedMemory Internal Test Signals. These signals are used Thermal Diode Positive / Negative. These signals arePower, Ground and No Connections1 Configuration Block Addresses General Configuration Block Register SummaryGeneral Configuration Block 32581C Offset Width Bits Type Name Reset Value ReferenceBall # Internal Test Signals Name Add’l Dependencies Other Signal Add’l DependenciesPMR27 FpcimonBall # IDE Signals Gpio and TFT Signals Name PP/ACB1/FPCI BitTFT Name Add’l Dependencies Ball # Gpio Signals LPC Signals Name Add’l Dependencies Rsvd Reserved. Write to32581CGeneral Configuration Block ReservedBit Description Interrupt Selection Register Intsel R/W Reset Value 00h Reset Value xxhOffset 39h-3Bh Offset 3ChWatchdog Timer Functional DescriptionWatchdog Registers Watchdog Interrupt3describes the Watchdog registers Usage HintsHigh-Resolution Timer High-Resolution Timer RegistersWatchdog Status Register Wdsts R/WC Reset Value 00h Offset 05h-07hReset Value xxxxxxxxh Tmclksel Timer Clock SelectTmen Timer Interrupt Enable Bit Description Offset 08h-0BhClock Generation Block Diagram Clock Generators and PLLsCrystal Oscillator Circuit Components 1 27 MHz Crystal OscillatorComponent Parameters Values Tolerance 2 GX1 Module Core Clock Internal Fast-PCI ClockCore Clock Frequency Strapped Core Clock FrequencyCore Logic Module Clocks SuperI/O ClocksVideo Processor Clocks Clock Registers Clock Generator Configuration8describes the registers of the clock generator and PLL 1514 ISA Outstanding FeaturesAB1C AB1D AB2C AB2D PC98 and Acpi Compliant Serial PortSerial Port 3 / Infrared IR Communication Port System Wakeup Control SWCInternal Internal Signals AccessModule Architecture Configuration Structure / Access SIO Configuration OptionsIndex-Data Register Pair LDN AssignmentsDefault Configuration Setup Address DecodingStandard Configuration Registers SIO Control and Configuration RegistersLogical Device Control and Configuration Registers Standard Logical Device Configuration RegistersStandard Configuration Registers 32581CSuperI/O Module Index F0h-FEh Logical Device Configuration R/WDMA Channel Select 1 R/W SIO Control and Configuration Registers SIO Control and Configuration Register MapIndex Type Name Power Rail Reset Value SID. SIO IDLogical Device Control and Configuration Relevant RTC Configuration RegistersRTC Configuration Registers LDN 01h System Wakeup Control Relevant SWC RegistersBase Address MSB register 10. IRCP/SP3 Configuration Register Relevant IRCP/SP3 Registers12. Serial Ports 1 and 2 Configuration Register Serial Ports 1 and 2 Configuration register11. Relevant Serial Ports 1 and 2 Registers LDN 03h and 08h Serial Ports 114. ACB1 and ACB2 Configuration Register LDN 05h and 06h ACCESS.bus Ports 1ACB1 and ACB2 Configuration register 13. Relevant ACB1 and ACB2 Registers16. Parallel Port Configuration Register 15. Relevant Parallel Port RegistersX32I External X32O Battery = 0.1 μF Real-Time Clock RTCBus Interface RTC Clock GenerationSignal Parameters External ElementsOscillator Startup External OscillatorAlarms Timekeeping Data FormatDaylight Saving Leap YearsRTC Power SupplyBT1 18. System Power States Interrupt Handling Battery-Backed RAMs and Registers108 RTC Registers 19. RTC Register Map20. RTC Registers Index Type NameIndex 04h Hours Register HOR R/W Index 05h Hours Alarm Register Hora R/W110 Index Programmable Month Alarm Register Mona R/W Index 0Ch RTC Control Register C CRC ROIndex Programmable Century Register CEN R/W AMD Geode SC3200 Processor Data Book 11121. Divider Chain Control / Test Selection 22. Periodic Interrupt Rate Encoding23. BCD and Binary Formats Rate Select Periodic Interrupt Divider Rate ms Chain Output0Eh 7Fh Battery-backed general-purpose Byte RAM 00h 7Fh Battery-backed general-purpose Byte RAMRTC General-Purpose RAM Map 24. Standard RAM Map 25. Extended RAM MapEvent Detection System Wakeup Control SWC26. Time Range Limits for Ceir Protocols SWC Registers 27. Banks 0 and 1 Common Control and Status Register MapType Name Value Offset Type Name Value29. Banks 0 and 1 Common Control and Status Registers 30. Bank 1 Ceir Wakeup Configuration and Control Registers Bit Description Ceir Wakeup Range 1 Registers Bank 1, Offset 0Ah IRWTR1L Register R/WCeir Pulse Change, Range 1, High Limit Ceir Wakeup Range 2 RegistersACCESS.bus Interface Data TransactionsABD ABC AMD Geode SC3200 Processor Data Book 119ABD MSB Acknowledge ACK CycleABC ACK Master Mode Acknowledge After Every Byte RuleArbitration on the Bus Addressing Transfer FormatsSending the Address Byte Master TransmitMaster Receive Master StopSlave Mode Configuration31. ACB Register Map ACB Registers32. ACB Registers MASTER. RO Reserved Inten Interrupt Enable Saen Slave Address EnableEN Enable Stop StopLegacy Functional Blocks Parallel Port33. Parallel Port Register Map for First Level Offset 34. Parallel Port Register Map for Second Level Offset35. Parallel Port Bit Map for First Level Offset 36. Parallel Port Bit Map for Second Level OffsetBits 128Uart Functionality SP1 and SP2 Type Name38. Bank Selection Encoding 39. Bank 1 Register Map40. Bank 2 Register Map 41. Bank 3 Register Map42. Bank 0 Bit Map 43. Bank 1 Bit MapRegister Bits Register Bits Offset45. Bank 3 Bit Map 44. Bank 2 Bit Map132 3.1 IR/SP3 Mode Register Bank Overview 46. Bank 0 Register MapIRCP/SP3 Register and Bit Maps 01h Register Throughout Offset 00h All Banks47. Bank Selection Encoding 48. Bank 1 Register Map49. Bank 2 Register Map BSR Bits Bank Selected Functionality51. Bank 4 Register Map 50. Bank 3 Register Map52. Bank 5 Register Map 54. Bank 7 Register Map 53. Bank 6 Register Map55. Bank 0 Bit Map 56. Bank 1 Bit Map 57. Bank 2 Bit Map58. Bank 3 Bit Map 59. Bank 4 Bit Map61. Bank 6 Bit Map 60. Bank 5 Bit Map62. Bank 7 Bit Map Feature List Config Integrated AudioVideo Processor Interface Low Pin Count LPC InterfaceFast-PCI Interface to External PCI Bus Pserial InterfaceIDE Configuration Registers PIO ModeIDE Controller Video Retrace InterruptPhysical Region Descriptor Format UltraDMA/33 Signal Definitions UltraDMA/33 ModeStop DMARDY# Strobe IdeiordyUniversal Serial Bus Sub-ISA Bus InterfaceIOCS0#/IOCS1# DocwSub-ISA Bus Cycles Sub-ISA Support of Delayed PCI Transactions146 5.4 I/O Recovery Delays REQ# GNT#FRAME# IRDY# TRDY# STOP# Bale ISA RD#, IOR# Sub-ISA Bus Data SteeringISA DMA 148PCI and Sub-ISA Signal Cycle Multiplexing Cycle Multiplexed PCI / Sub-ISA BallsROM Interface PCIFRAME# TRDY#, IRDY# ROMCS#, DOCCS# IOCS0#, IOCS1# PAR DEVSEL#,STOP#DMA Controller DMA ChannelsDMA Transfer Modes DMA Controller RegistersDMA Transfer Types DMA PriorityProgrammable Interval Timer DMA Addressing CapabilityDMA Page Registers and Extended Addressing DMA Address GenerationPIC Interrupt Mapping Programmable Interrupt ControllerMaster MappingPIC Interrupt Sequence PIC I/O RegistersPIC Shadow Register PCI Compatible InterruptsFast Keyboard Gate Address 20 and CPU Reset Keyboard Support7.1 I/O Port 092h System Control 7.2 I/O Port 061h System ControlPower Management Logic Wakeup Events Capability Power Planes vs. Sleep/Global States Power Planes Control Signals vs Sleep StatesPower Management Events Power Button Power Button OverrideThermal Monitoring AMD Geode SC3200 Processor Data Book 159Power Management Programming CPU Power ManagementAPM Support Suspend ModulationSave-to-Disk Volt SuspendAMD Geode SC3200 Processor Data Book 161 Peripheral Power Management Device Idle Timers and TrapsGeneral Purpose Timers Acpi Timer RegisterModule Power Management SMI Status Reporting RegistersF1BAR0+I/O Device Power Management Programming Summary Power Management Programming SummaryLocated at F0 Index xxh Unless Otherwise Noted F1BAR0+I/OGpio Interface Integrated Audio11. Physical Region Descriptor Format ByteAudio Data Buffer SizePRD1 PRD2 PRD3Codec Configuration/Control Registers Codec Command Register12.2 AC97 Codec Interface Codec Gpio Status and Control RegistersTrap SMI Enable Register VSA Technology Support HardwareVSA Technology Audio SMI Related RegistersModule Core Logic Module IRQ Configuration Registers Internal IRQ Enable RegisterInternal IRQ Control Register LPC Interface12. Cycle Types 13. PCI Configuration Address Register 0CF8h PCI Configuration Space and Access MethodsRegister Descriptions Register Summary Ter’s reset values and page references where the bit forMats are found Core Logic Module Register Summary 32581C Width Reset Reference F0 Index BitsAMD Geode SC3200 Processor Data Book 175 32581CCore Logic Module Register Summary 17615. F0BAR0 Gpio Support Registers Summary 16. F0BAR1 LPC Support Registers SummaryF0BAR0+ F0BAR1+18. F1BAR0 SMI Status Registers Summary F1BAR0+F1BAR1+ 19. F1BAR1 Acpi Support Registers SummaryAMD Geode SC3200 Processor Data Book 179 Width Reset Reference F2 Index Bits 180Width Reset Reference F3 Index Bits 21. F2BAR4 IDE Controller Support Registers Summary22. F3 PCI Header Registers for Audio Support Summary F2BAR4+Width Reset 23. F3BAR0 Audio Support Registers SummaryF3BAR0+ 182Width Reset Reference F5 Index Bits 25. F5BAR0 I/O Control Support Registers SummaryF5BAR0+ AMD Geode SC3200 Processor Data Book 18326. Pciusb USB PCI Configuration Register Summary Name Reset ValuePciusb Width Reference Index BitsUSBBAR0 27. Usbbar USB Controller Registers SummaryAMD Geode SC3200 Processor Data Book 185 DMA Page Registers Table 28. ISA Legacy I/O Register Summary186 Programmable Interval Timer Registers Table Port Type Name ReferenceProgrammable Interrupt Controller Registers Table Keyboard Controller Registers TableBridge, GPIO, and LPC Registers Function Chipset Register SpaceGeneral Remarks Data Parity Detected. This bit is set when Index 06h-07h PCI Status Register R/WAMD Geode SC3200 Processor Data Book 189 Index 0Eh PCI Header Type RO Reset Value 80h Bit Description Index 08hIndex 09h-0Bh Index 0ChPCI Subtractive Decode AMD Geode SC3200 Processor Data Book 191Reset Control Register R/W Reset Value 01h Index 42hIndex 43h 192Index 45h Index 46hIndex 47h AMD Geode SC3200 Processor Data Book 193Reset Value FFFFFFFFh Reset Value 7BhPIT Software Reset PIT Counter 1 EnableGenerate SMI on A20M# Toggle ROM/AT Logic Control Register R/W Reset Value 98hAMD Geode SC3200 Processor Data Book 195 Bit Description Index 54h-59h Index 5AhIndex 5Bh Decode Control Register 2 R/W 196INTB# Ball C26 Target Interrupt INTA# Ball D26 Target InterruptINTD# Ball AA2 Target Interrupt INTC# Ball C9 Target Interrupt198 Index 72h Chip Select 1 Positive Decode IOCS1#Index 73h Index 76hIndex 7Ch-7Fh DOCCS# Control Register R/W 3127DiskOnChip Chip Select Positive Decode DOCCS# 200Index 81h Power Management Enable Register 2 R/W AMD Geode SC3200 Processor Data Book 201202 Power Management Enable Register 3 R/W Reset Value 00h Keyboard/Mouse Access TrapParallel/Serial Access Trap AMD Geode SC3200 Processor Data Book 203Floppy Disk Access Trap Primary Hard Disk Access TrapIndex 83h Power Management Enable Register 4 R/W 204Index 84h Second Level PME/SMI Status Mirror Register 1 RO AMD Geode SC3200 Processor Data Book 205206 AMD Geode SC3200 Processor Data Book 207 Index 88h General Purpose Timer 1 Count Register R/W 208Re-trigger General Purpose Timer 1 on Floppy Disk Activity AMD Geode SC3200 Processor Data Book 209Index 8Dh Video Speedup Timer Count Register R/W Index 8Bh General Purpose Timer 2 Control Register R/W210 Index 93h Index 8Fh-92hAMD Geode SC3200 Processor Data Book 211 Index 9Ah-9Bh Floppy Disk Idle Timer Count Register R/W Index 97hIndex 98h-99h 212Index A6h-A7h Video Idle Timer Count Register R/W Index A8h-A9h Video Overflow Count Register R/WIndex AEh CPU Suspend Command Register WO Index AFh Suspend Notebook Command Register WOIndex B0h-B3h Index B4hIndex BAh PIT Shadow Register RO Index B9h PIC Shadow Register ROAMD Geode SC3200 Processor Data Book 215 Index BCh Clock Stop Control Register R/W Reset Value 00h Reserved. Set to CPU Clock StopIndex BDh-BFh Index C0h-C3hBit Description Index CCh MaskIndex CDh Index CEhIndex EDh-F3h Index F4hIndex F5h Second Level PME/SMI Status Register 2 RC 218Index F6h Second Level PME/SMI Status Register 3 RC AMD Geode SC3200 Processor Data Book 219Index F7h Second Level PME/SMI Status Register 4 RC 220Index F8h-FFh 30. F0BAR0+I/O Offset Gpio Configuration Registers I/O mapped registers accessed through F0BAR0Gpio Support Registers Ration registers are located. -29gives the bit formatsF0BAR0+I/O Offset 18h is set, this edge generates a PME Offset 14h-17h GPDI1 Gpio Data In 1 Register ROAMD Geode SC3200 Processor Data Book 223 Bank 224AMD Geode SC3200 Processor Data Book 225 31. F0BAR1+I/O Offset LPC Interface Configuration Registers LPC Support Registers3121 Reserved. Set toAMD Geode SC3200 Processor Data Book 227 228 Reserved Serial IRQ Enable Serial IRQ Interface ModeNumber of IRQ Data Frames AMD Geode SC3200 Processor Data Book 229230 LPC Game Port 1 Address Select. Selects I/O Port LPC Game Port 0 Address Select. Selects I/O PortLPC Floppy Disk Controller Address Select. Selects I/O Port LPC Midi Address Select. Selects I/O Port232 Bit SMI Status and Acpi Registers Function 32. F1 PCI Header Registers for SMI Status and Acpi SupportSMI Status Support Registers 33. F1BAR0+I/O Offset SMI Status RegistersAMD Geode SC3200 Processor Data Book 235 Offset 02h-03h Top Level PME/SMI Status Register RO/RC Suspend Modulation Enable Mirror. Read to Clear236 AMD Geode SC3200 Processor Data Book 237 Offset 04h-05h 238AMD Geode SC3200 Processor Data Book 239 These addresses should not be written Offset 1Ch-1Fh Offset 0Ah-1Bh240 3124 Offset 24h-27h External SMI Register R/WAMD Geode SC3200 Processor Data Book 241 242 AMD Geode SC3200 Processor Data Book 243 50h-FFh Offset 28h-4Fh Not Used Reset Value 00h244 Offset 06h Smicmd OS/BIOS Requests Register R/W 34. F1BAR1+I/O Offset Acpi Support RegistersAcpi Support Registers Clkval Clock Throttling Value. CPU duty cycle1412 246Offset 0Ah-0Bh PM1AEN PM1A PME/SCI Enable Register R/W 1511Offset 0Ch-0Dh PM1ACNT PM1A Control Register R/W AMD Geode SC3200 Processor Data Book 247248 AMD Geode SC3200 Processor Data Book 249 250 AMD Geode SC3200 Processor Data Book 251 Gpwio Control Register 2 R/W Reset Value 00h Reserved Gpwio Control Register 1 R/W Reset Value 00h252 Gpwio Data Register R/W Reset Value 00h Offset 17h3117 Reserved AMD Geode SC3200 Processor Data Book 253Offset 21h-FFh 254IDE Controller Registers Function Bit Description Index 30h-3Fh PIOMODE. PIO mode256 Reset Value 00009172h Reset Value 00077771h3024 AMD Geode SC3200 Processor Data Book 257Bit Description Index 50h-53h Index 58h-5BhIndex 60h-FFh 258IDE Controller Support Registers AMD Geode SC3200 Processor Data Book 259Offset 09h Offset 0AhOffset 0Bh Offset 0Ch-0Fh37. F3 PCI Header Registers for Audio Configuration Audio Registers Function38. F3BAR0+Memory Offset Audio Configuration Registers Audio Support Registers2921 Offset 04h-07hAMD Geode SC3200 Processor Data Book 263 264 Offset 14h-17h Trap SMI and Fast Write Status Register RO/RC AMD Geode SC3200 Processor Data Book 265266 Reserved. Must be set to 32581CCore Logic Module Audio Registers Function Mask Internal IRQ15. Write OnlyMask Internal IRQ14. Write Only Mask Internal IRQ11. Write OnlyMask Internal IRQ4. Write Only Mask Internal IRQ3. Write OnlyAssert Masked Internal IRQ14 Reserved. Set to Assert Masked Internal IRQ12Bit Description Assert Masked Internal IRQ1 270Audio Bus Master 1 Command Register R/W Reset Value 00h Offset 29h Audio Bus Master 1 SMI Status Register RCOffset 2Ah-2Bh Offset 2Ch-2FhAudio Bus Master 2 Command Register R/W Reset Value 00h Offset 31h Audio Bus Master 2 SMI Status Register RCOffset 32h-33h Offset 34h-37hAudio Bus Master 3 Command Register R/W Reset Value 00h Offset 39h Audio Bus Master 3 SMI Status Register RCOffset 3Ah-3Bh Offset 3Ch-3FhAudio Bus Master 4 Command Register R/W Reset Value 00h Offset 41h Audio Bus Master 4 SMI Status Register RCOffset 42h-43h Offset 44h-47hAudio Bus Master 5 Command Register R/W Reset Value 00h Offset 49h Audio Bus Master 5 SMI Status Register RCOffset 4Ah-4Bh Offset 4Ch-4FhBus Expansion Interface Function 39. F5 PCI Header Registers for X-Bus ExpansionCore Logic Module X-Bus Expansion Interface Function 32581C Bit Description Index 1Ch-1FhIndex 20h-23h Index 24h-27hIndex 48h-4Bh F5BAR2 Mask Address Register R/W Index 4Ch-4Fh F5BAR3 Mask Address Register R/WIndex 50h-53h F5BAR4 Mask Address Register R/W Index 54h-57h F5BAR5 Mask Address Register R/WBit Description Index 64h-67h AMD Geode SC3200 Processor Data Book 279Base address that allows PCI access to additional I/O Con 40. F5BAR0+I/O Offset X-Bus Expansion RegistersBus Expansion Support Registers F5 Index 10h, Base Address Register 0 F5BAR0 setIostrapidselselect Idsel Strap Override Iotestporten Debug Test Port EnableAMD Geode SC3200 Processor Data Book 281 41. Pciusb USB PCI Configuration Registers USB Controller Registers PciusbBit Description 282Reset Value 08h Index 0Dh Latency Timer Register R/WCore Logic Module USB Controller Registers Pciusb 32581C Index 06h-07h Status Register R/WReset Value 0E11h Reset Value A0F8hReset Value 50h Index 30h-3Bh42. USBBAR+Memory Offset USB Controller Registers AMD Geode SC3200 Processor Data Book 285HcInterruptEnable Register R/W Reset Value = 00000000h OwnershipChangeEnableRootHubStatusChangeEnable FrameNumberOverflowEnableOffset 28h-2Bh 287Reset Value = 00000628h Reset Value = 01000003hBit Description Offset 34h-37h Offset 38h-3BhRead LocalPowerStatusChange. Not supported. Always read Offset 50h-53h HcRhStatus Register R/W3018 AMD Geode SC3200 Processor Data Book 289HcRhPortStatus1 Register R/W Reset Value = 00000000h Read PortResetStatusRead PortSuspendStatus 290 AMD Geode SC3200 Processor Data BookBit Description Read PortEnableStatus Read CurrentConnectStatus1510 AMD Geode SC3200 Processor Data Book 291292 Reset Value = xxh Offset 60h-9FhOffset 100h-103h 319 Reserved. Read/Write 0sReset Value = 000000xxh Offset 104h-107h318 Reserved. Read/Write 0s 294ISA Legacy Register Space 43. DMA Channel Control RegistersPriority Mode Timing Mode32581CCore Logic Module ISA Legacy Register Space WriteTransfer Mode Channel Number Mode SelectBit Description Port 00Bh Address DirectionUndefined Write DMA Command Register, Channels298 Bit Description Port 0D2h Port 0D4hPort 0D6h Port 0D8h44. DMA Page Registers 45. Programmable Interval Timer Registers Current Counter Mode BCD Mode Bit Description Port 042h WriteCounter Value Read Port 043h R/W46. Programmable Interrupt Controller Registers Poll Command Register Read ModeBit Description IRQ2 / IRQ10 Mask IRQ1 / IRQ9 MaskInterrupt Service Register IRQ7 / IRQ15 In-Service IRQ6 / IRQ14 In-ServiceIRQ5 / IRQ13 In-Service IRQ4 / IRQ12 In-Service47. Keyboard Controller Registers 48. Real-Time Clock Registers 49. Miscellaneous Registers308 General Features Video Input Port VIPHardware Video Acceleration Graphics-Video Overlay and BlendingVIP Mixer/BlenderFunctional Description Video SupportVBI Support AMD Geode SC3200 Processor Data Book 311Active Video Video Input Port VIP Direct Video ModeGenLock Capture Video Mode BobProgram the VIP bus master address registers Program other VIP bus master support registersWeave AMD Geode SC3200 Processor Data Book 315Ping-pongs between the two buffers during runtime Field Interrupt Capture VBI Mode316 Video Block Video Input FormatterLine Buffer AMD Geode SC3200 Processor Data Book 317Filtering Horizontal Downscaler with 4-Tap FilteringHorizontal Downscaler Line Buffers Formatter2.5 2-Tap Vertical and Horizontal Upscalers AMD Geode SC3200 Processor Data Book 319Mixer/Blender Block RGBRAM YUVValid Mixing/Blending Configurations YUV to RGB CSC in Video Data PathGamma Correction Color/Chroma KeyColor/Chroma Key and Mixer/Blender Graphics WindowVideo Window Cursor WindowTruth Table for Alpha Blending Mixing/Blending OperationColor CHROMASEL112. Color Key and Alpha Blending Logic 324Power Sequence TFT InterfaceHSYNC, VSYNC, TFTDE, Tftdck T1 is a programmable multiple of frame time T0+T1Integrated PLL 326F4 PCI Header Registers for Video Processor Support Summary F4BAR0 Video Processor Configuration Registers SummaryF4BAR0+ 32581CVideo Processor Module Register Summary 328F4BAR2+ F4BAR2 VIP Support Registers SummaryAMD Geode SC3200 Processor Data Book 329 Reset Value 0504h Reset Value 030000hVideo Processor Registers Function 3112 VIP Base Address 110 Address Range. Read OnlyIndex 3Eh-FFh Reserved AMD Geode SC3200 Processor Data Book 331Video Configuration Register R/W Reset Value 00000000h EN42X Enable 42x Format. Allows format selectionVideo Processor Support Registers F4BAR0 To 0 or 1 should be written with a value that is readReserved. Write as read Reserved Offset 04h-07h Display Configuration Register R/WAMD Geode SC3200 Processor Data Book 333 Bit Description Offset 08h-0Bh Video X Position Register R/W 334Bit Description Offset 14h-17h Video Color Key Register R/W Offset 20h-23hReset Value 00001400h Reserved PLL2PWREN PLL2 Power-Down EnableBit Description Offset 28h-2Bh Clkdivsel Clock Divider SelectReserved Signen Signature Enable DTS Downscale Type SelectOffset 40h-43h Video Downscaler Coefficient Register R/W FLTCO4 Filter Coefficient 4. For the tap-4 filterReserved Set to 338Offset 54h-57h Offset 50h-53hAMD Geode SC3200 Processor Data Book 339 Enable Alpha Window Disable Alpha Window 158 340AMD Geode SC3200 Processor Data Book 341 342 Bit Description Offset 90h-93h Offset 94h-97hALPHA3VAL Value for Alpha Window ALPHA2VAL Value for Alpha WindowReserved. Set to Genlocktouten GenLock Timeout Enable Ctgenlocken Enable Continuous GenLock FunctionReserved. Set to Offset 424h-427h 3121 Reserved 200F4BAR2+Memory Offset VIP Configuration Registers VIP Support Registers F4BAR2F4 Index 18h, Base Address Register 2 F4BAR2 points to AMD Geode SC3200 Processor Data Book 345Capture Store to Memory VBI Data Capture Store to Memory Video DataReserved. Read Only Current Field. Read Only 2322Bit Description Video Data Capture Active. Read Only Run Status. Read Only3110 Reserved Start of each field Offset 14h-17hOffset 44h-47h VBI Data Even Base Register R/W Offset 48h-4Bh VBI Data Pitch Register R/WJtag Mode Instruction Support Testability JtagMandatory Instruction Support Optional Instruction Support350 General Specifications Power/Ground Connections and DecouplingElectro Static Discharge ESD Absolute Maximum RatingsOperating Conditions Symbol Parameter Min Typ Max Unit CommentsVSS Power Planes of External Interface Signals Power Plane Signal Names VCC Balls VSS BallsPower State Parameter Definitions DC CurrentDC Characteristics for On State Symbol ParameterNote Min Typ Max Unit Comments DC Characteristics for Active Idle, Sleep, and Off StatesBall Capacitance and Inductance Pull-Up and Pull-Down Resistors Balls with PU/PD ResistorsVIO External PU or PD resistorDC Characteristics Symbol Description ReferenceWire 10. Buffer TypesInbtn DC Characteristics Inab DC CharacteristicsInpci DC Characteristics Instrp DC Characteristics INT DC CharacteristicsInts DC Characteristics INTS1 DC CharacteristicsInusb DC Characteristics ODn DC CharacteristicsOdpci DC Characteristics Op/n DC CharacteristicsOpci DC Characteristics Ousb DC CharacteristicsAC Characteristics 11. Default Levels for Measurement Switching ParametersSymbol Parameter Value CLKOutputs Memory Controller InterfaceInputs 32581CElectrical Specifications 12. Memory Controller Timing ParametersSDCLK30, Sdclkout high time 233 MHz 266 MHz 364T1, t2, t3 SDCLK30 Control Output, MA120BA10, MD630 MD630 Data Valid Read DataVideo Port 13. Video Input Port Timing Parameters Vpckin VrefTFT Interface 14. TFT Timing Parameters Tftdck rise/fall time between 0.8VTftdck period time multiplexed on IDE Tftdck period time multiplexed on15. ACCESS.bus Input Timing Parameters ACCESS.bus Interface16. ACCESS.bus Output Timing Parameters AB1D AB2D AB1C AB2CAB1D AB2D AB1C AB1D AB2D AB1C AB2C370 17. PCI AC Specifications PCI Bus Interface64VIO 16VIOEquation a Equation B 18. PCI Clock Parameters Pciclk 0.4 V IO19. PCI Timing Parameters 20. Measurement Condition Parameters Symbol Value Unit CommentsMeasurement and Test Conditions Power SignalsInput Valid Ms typSymbol Parameter Bits Type Comments Sub-ISA Interface21. Sub-ISA Timing Parameters Bus Width MinBus Width Min Max Symbol Parameter Bits Type Comments DOCR#/IOR#ROMCS#/DOCCS# IOR#/RD#/TRDE#MEMR#/DOCR# IOW#/WR# MEMW#/DOCW#DOCCS#/ROMCS# IOCS10#IOW#/WR# MEMW#/DOCW# TRDE# D150LPC Interface 22. LPC and Serirq Timing Parameters IDE signals fall time from 0.9V IO to 0.1V IO = 40 pF IDE signals rise time from 0.1V IO to 0.9V IO = 40 pFIDE Interface 23. IDE General Timing Parameters IDERST# pulse widthMode Symbol Parameter Unit Comments 24. IDE Register Transfer to/from Device Timing ParametersCycle time min Width 8-bit minAddr valid1 IDEIOR0# IDEIOW0# Write IDEDATA70Read IDEDATA70 IDEIORDY0 2,325. IDE PIO Data Transfer to/from Device Timing Parameters AMD Geode SC3200 Processor Data Book 385Read IDEDATA150 IDEIOR0# IDEIOW0# Write IDEDATA150386 26. IDE Multiword DMA Data Transfer Timing Parameters IDEDREQ0 IDEDACK0# IDEIOR0# IDEIOW0# IDECS10#388 27. IDE UltraDMA Data Burst Timing Parameters Mode Symbol Parameter Min Max Unit CommentsAMD Geode SC3200 Processor Data Book 389 IDEREQ0 STOP0IDEIOR0# HDMARDY0# IDEIRDY0 DSTROBE0IDEIRDY0 DSTROBE0 at device IDEDATA150 at device IDEIRDY0 DSTROBE0 at hostIDEDATA150 at host AMD Geode SC3200 Processor Data Book 391IDEDREQ0 device IDEDACK0 host IDEIOW0STOP0 hostIDEIOR0HDMARDY0 392IDEIOW0# STOP0# IDEDREQ0 deviceAMD Geode SC3200 Processor Data Book 393 IDEIOW0# STOP0# host IDEIOR0# HDMARDY0# host IDEIRDY0 DSTROBE0 device IDEDATA150 deviceIDECS01# IDEADDR20DevicetUI IDEDACK0# host IDEIOW0# STOP0# hostIDEIORDY0 DDMARDY0 device IDEIOR0# HSTROBE0# hostHSTROBE0# At hostIDEDATA150 At host IDEIOR0# HSTROBE0# at device IDEDATA150 at deviceIDEDREQ0 device IDEDACK0# host IDEIOW0# STOP0# host IDEIORDY0# DDMARDY0#IDEIOR0# HSTROBE0# AMD Geode SC3200 Processor Data Book 397IDEDATA150 host IDEADDR20 IDECS01# IDEIORDY0# DDMARDY0# device398 IDEDATA150 host IDECS01# IDEADDR20 IDEDREQ0 device IDEDACK0 host IDEIOW0# STOP0# hostAMD Geode SC3200 Processor Data Book 399 Full Speed Receiver EOP Width Note Low Speed Source NoteSource EOP width Host upstreamReceiver data jitter tolerance for paired Low Speed Receiver EOP Width NoteRise Time Fall Time Differential Data LinesDifferential Data Lines Crossover Points 2.0 Consecutive TransitionsDifferential Data to SE0 Skew Data Crossover LevelEOP Width Differential Crossover Points Data LinesModulation signal period TCPN + Transmitter Sharp-IR and Consumer Remote ControlSIR signal pulse width Setting of the Rxhsc bit bit 5 of the Rccfg registerMIR Fast IR Port 30. Fast IR Port Timing ParametersFIR Busy ACK# STB#32. Enhanced Parallel Port Timing Parameters Symbol Parameter MinUnit Comments 33. ECP Forward Mode Timing Parameters Extended Capabilities Port ECPAFD# Busy34. ECP Reverse Mode Timing Parameters BUSY#Audio Interface AC97 35. AC Reset Timing Parameters AC97RST# inactive to Bitclk 162.8 Startup delaySync inactive to Bitclk startup 162.8 Delay AC97RST# active low pulse width37. AC97 Clocks Parameters AC97CLK Vold38. AC97 I/O Timing Parameters SDATAOUT/SYNC SDATAIN, SDATAIN239. AC97 Signal Rise and Fall Timing Parameters 40. AC97 Low Power Mode Timing Parameters End of Slot 2 to Bitclk Sdatain lowSlot Bitclk SdataoutPower Management Interface Power management event to ONCTL# Assertion41. PWRBTN# Timing Parameters ONCTL# PWRBTN#PWRBTN# ONTCL# PWRCNT21 POR# POR# 32KHZ AMD Geode SC3200 Processor Data Book 417TDI, TMS setup time Non-test inputs setup timeJtag Interface 45. Jtag Timing Parameters TDI, TMS hold timeOutput Signals Input SignalsTDI TMS TDO AMD Geode SC3200 Processor Data Book 419420 ΘJC ×C/W Thermal CharacteristicsCase-to-Ambient Thermal Resistance Example @ 85C Heatsink Considerations ExampleAssume P max = 5W and TA max = 40C Therefore Assume P max = 9W and TA max = 40C ThereforePhysical Dimensions AMD Geode SC3200 Processor Data Book 423BGU481 Package Bottom View 424Order Information Ordering Part Number Core FrequencyMHz Degree C PackageTable A-1. Revision History Data Book Revision HistoryRevision # Revisions / Comments Appendix a Data Book Revision History 32581C 89V toAMD Geode SC3200 Processor Data Book 427

6.4.5.1 X-Bus Expansion Support Registers

F5 Index 10h, Base Address Register 0 (F5BAR0) set the

base address that allows PCI access to additional I/O Con-

Table 6-40. F5BAR0+I/O Offset: X-Bus Expansion Registers

Bit

Reserved.

IO_ENABLE_SIO_IR (Enable Integrated SIO Infrared).

Disable.

Enable.

26:25

Reserved. Set to 0.

IO_USB_SMI_EN (USB SMI Configuration). Allow USB-generated SMIs.