AMD SC3200 manual Video Input Port VIP, Direct Video Mode, GenLock

Video Processor Module		32581C
7.2.1	Video Input Port (VIP)	Video data is clocked out using the GX1’s Video port clock
The VIP block is designed to interface the SC3200 with		(75, 116, or 133 MHz GX1 core clock divided by 2 or 4).
external video processors (e.g., Philips PNX1300 or Sigma		7.2.1.1 Direct Video Mode
Designs EM8400) or external TV decoders (e.g., Philips
		As stated previously, Direct Video mode is on by default so
SAA7114). It inputs CCIR-656 Video and raw VBI data
sourced by those devices, decodes the data, and delivers		no registers need to be programmed to support this mode
the data directly to the Video Formatter (Direct Video		other than to select the direct video data at the video mux.
mode) or to the GX1 module’s video frame buffer (Capture		The video mux control register is located at F4BAR0+Mem-
Video/VBI modes). Figure 7-4shows a diagram of the VIP		ory Offset 400h[1:0].
block.		Direct Video mode while supported is not an optimal mode
From the VIP block’s perspective, Direct Video mode is		of operation. This mode supports only one vertical resolu-
always on. There are no registers that enable/disable		tion and refresh rate, which is that of the incoming data.
Direct Video mode. The data source selected at the video		Horizontal resolution can be scaled if desired. Since the
mux (F4BAR0+Memory Offset 400h[1:0]) determines if the		incoming data has odd and even fields, incoming line must
data from the VIP interface is moved directly or must be		be doubled for it to display properly. This is equivalent to
captured.		the Bob technique which is explained later in this section.
Two FIFOs in the VIP block support the efficient movement		GenLock
of Video and VBI data. For Capture Video/VBI modes, a		Because video input data from the VIP is sent directly, with-
128-byte FIFO buffers both Video and raw VBI data pro-
		out significant buffering frame-to-field synchronization is
cessed by the CCIR-656 decoder. For Direct Video mode,
		required with the GX1 module’s graphics data. This syn-
there is	a 2048-byte FIFO that buffer the CCIR-656
		chronization is known as GenLock. The GenLock registers

decoder’s video data. The FIFOs are also used to provide	are located at F4BAR0+Memory Offset 420h and 424h.
clock domain changes. The VIP interface clock (nominally
27 MHz) is the input clock domain for both FIFOs. For the
Capture Video/VBI FIFO, the data is clocked out using the
FPCI clock (33 or 66 MHz). For the Direct Video FIFO, the

VSYNC		Stop DCLK
	GenLock
VIP_VSYNC
	Control

VIP
Data	CCIR-656
	Decoder
VIP

Capture Video/VBI

Controller and

Bus Master

Capture Video/VBI

FIFO

Direct Video

FIFO

Fast-PCI Clock

Capture Video/VBI Data

GX1 Video Clock

Direct Video Data

Fast
X-Bus	Fast-PCI	GX1
to
Fast-PCI		Module
Bridge

Video or VBI Data

to Video

Video Formatter Mux

Clock

Direct Video/VBI

Controller

F4BAR2
Control
Registers	VIP

Figure 7-4. VIP Block Diagram

AMD Geode™ SC3200 Processor Data Book 313