Chapter 3
BIOS Configuration
Chipset Features Setup - Default Settings Chart
Setting Option | BIOS Default | Setup Default |
Bank 0/1 DRAM Timing | SDRAM 10ns | SDRAM 10ns |
Bank 2/3 DRAM Timing | FP/EDO 70ns | FP/EDO 70ns |
Bank 4/5 DRAM Timing | FP/EDO 70ns | FP/EDO 70ns |
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SDRAM Cycle Length | 3 | 3 |
DRAM Read Pipeline | Disabled | Enabled |
Cache Rd+CPU Wt Pipeline | Disabled | Enabled |
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Cache Timing | Fast | Fast |
Video BIOS Cacheable | Disabled | Enabled |
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System BIOS Cacheable | Disabled | Enabled |
Memory Hole At 15Mb Addr | Disabled | Disabled |
AGP Aperture Size | 64M | 64M |
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OnChip USB | Enabled | Enabled |
USB Keyboard Support | Disabled | Disabled |
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Current CPU Temperature | 35C / 95F | 35C / 95F |
Current System Temp. | 27C / 80F | 27C / 80F |
Current CPUFAN Speed | 0 RPM | 0 RPM |
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Current SYSFAN Speed | 0 RPM | 0 RPM |
Vcore | 2.40V | 2.40V |
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3.3V | 3.31V | 3.31V |
5V | 4.95V | 4.95V |
12V | 12.12V | 12.12V |
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Bank 0/1, 2/3, 4/5 DRAM Timing
The system board designer must select the proper value for these fields, according to the specifications of the installed DRAM chips. Turbo mode reduces CAS access time by 1 clock tick.
SDRAM Cycle Length
This field sets the CAS latency timing.
DRAM Read Pipeline
Select Enabled to pipeline reads from system memory. Pipelining improves system performance.
Cache Rd+CPU Wt Pipeline
Select Enabled to pipeline reads from cache memory and writes from the CPU. Pipelining improves system performance.
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