AMD specifications Compatible with Existing 32-Bit Code Base, AMD64 Technology Packages, 32816

– ECC checking with double-bit detect and single-bit correct

AMD Turion™ 64 Mobile Technology Product Data Sheet

•Compatible with Existing 32-Bit Code Base

	– Including support for SSE, SSE2, SSE3*, MMX™,	754-Pin Package Specific Features
	3DNow!™ technology, and legacy x86 instructions
	*SSE3 supported by Rev. E and later processors	• Refer to the AMD Functional Data Sheet,
	– Runs existing operating systems and drivers
			754-Pin Package, order# 31410, for functional,
	– Local APIC on the chip		mechanical, and electrical details of 754-pin
•	AMD64 Technology		packages.
	– AMD64 technology instruction set extensions	•	Packaging
	– 64-bit integer registers, 48-bit virtual addresses,		– 754-pin lidless micro PGA
	40-bit physical addresses		–	1.27-mm pin pitch
	– Eight additional 64-bit integer registers (16 total)		– 29 x 29-row pin array
	– Eight additional 128-bit SSE registers (16 total)		– 40 mm x 40 mm organic substrate
•	Enhanced Virus Protection		– Organic C4 die attach
	– No Execute (NX) bit in page-translation tables	•	Integrated Memory Controller
	specifies whether code can be executed from the		–	Low-latency, high-bandwidth
	page		– 72-bit DDR SDRAM at 100, 133, 166, and 200 MHz
• HyperTransport™ Technology to I/O Devices			– Supports up to two unbuffered SO-DIMMs

–One 16-bit link supporting speeds up to 800 MHz (1600 MT/s) or 3.2 Gbytes/s in each direction

•64-Kbyte 2-Way Associative ECC-Protected L1 Data Cache

–Two 64-bit operations per cycle, 3-cycle latency

•64-Kbyte 2-Way Associative Parity-Protected L1 Instruction Cache

–With advanced branch prediction

•16-Way Associative ECC-Protected

L2 Cache

–Exclusive cache architecture—storage in addition to L1 caches

–Up to 1 Mbyte per L2 cache

–1 Mbyte and 512-Kbyte options

•Machine Check Architecture

–Includes hardware scrubbing of major ECC-protected arrays

•Electrical Interfaces

–HyperTransport™ technology: LVDS-like differential, unidirectional

–DDR SDRAM: SSTL_2 per JEDEC specification

–Clock, reset, and test signals also use DDR SDRAM-like electrical specifications.

•Power Management

–Multiple low-power states including Deeper Sleep (C3 with AltVID)

–System Management Mode (SMM)

–ACPI compliant, including support for processor performance states

–AMD PowerNow!™ technology is designed to dynamically switch between multiple low-power states based on application performance requirements.

Publication #	32816	Revision:	3.05
Issue Date:	September 2006

Advanced Micro Devices