Analog Devices ADSST-SALEM-3T ADSST-218X COMMON-MODE Pins, Pin Name No. of Pins, Function

ADSST-SALEM-3T

ADSST-218X COMMON-MODE PINS

Table 2.

Pin Name	No. of Pins	I/O
	1	O
BG
	1	O
BGH
	1	O
BMS
	1	I
BR
	1	O
CMS
	1	O
DMS
	1	O
IOMS
	1	O
PMS
	1	O
RD
	1	I
RESET
	1	O
WR
	1	I
IRQ2/
PF7		I/O
	1	I
IRQL1/
PF6		I/O
	1	I
IRQL0/
PF5		I/O
	1	I
IRQE/
PF4		I/O
MODE A	1	I
PF0		I/O
MODE B	1	I
PF1		I/O
MODE C	1	I
PF2		I/O
MODE D	1	I
PF3		I/O
CLKIN, XTAL	2	I
CLKOUT	1	O
EZ-Port	9	I/O
FI, FO
FL0, FL1, FL2	3	O
GND	10	I
IRQ1:0
	1	I
PWD
SPORT0	5	I/O
SPORT1	5	I/O
PWDACK	1	O
VDDEXT	4	I
VDDEXT	7	I
VDDINT	2	I
VDDINT	4	I

Function

Bus Grant Output

Bus Grant Hung Output

Byte Memory Select Output

Bus Request Input

Combined Memory Select Output

Data Memory Select Output

Memory Select Output

Program Memory Select Output

Memory Read Enable Output

Processor Reset Input

Memory Write Enable Output

Edge- or Level-Sensitive Interrupt Request1 Programmable I/O Pin

Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin

Mode Select Input−Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input−Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input−Checked only during RESET Programmable I/O Pin during Normal Operation Mode Select Input−Checked only during RESET Programmable I/O Pin during Normal Operation Clock or Quartz Crystal Input

Processor Clock Output For Emulation Use Flag In, Flag Out2 Output Flags

Power and Ground

Edge- or Level-Sensitive Interrupts Power-Down Control Input Serial Port I/O Pins

Serial Port I/O Pins Power-Down Control Output External VDD (2.5 V or 3.3 V) Power (LQFP) External VDD (2.5 V or 3.3 V) Power (Mini-BGA) Internal VDD (2.5 V) Power (LQFP)

Internal VDD (2.5 V) Power (Mini-BGA)

1Interrupt/flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag.

2SPORT configuration determined by the DSP System Control register. Software configurable.

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