Limitations of SAT

Although SAT is a powerful tool, please keep in mind the following :

1.The loop gain Bode plot and phase margin predicted by SAT are valid when the module is operating in continuous conduction mode (CCM). Therefore, make sure that RL is sufficiently low enough to guarantee a load current that leads to CCM operation. Modules with synchronous rectifier based output stages operate in CCM throughout the entire load current range.

2.It is assumed that the module input voltage is at the nominal value, e.g. 48V for xWxxx, 24V for xCxx modules, etc. The loop response and phase margin will be

different if the input voltage is not at the nominal value. However, for stability assessment purposes, since there are usually requirements for margins of >45° and 12dB, performing a stability analysis at nominal voltage of 48V is typically sufficient.

3.For buck derived converter topologies, the sensitivity of voltage loop response on load variations is small. Therefore, SAT captures the loop response over load variations, from CCM limit to full load, with reasonable accuracy. Future releases of SAT will address the effect of input voltage variations on the stability margins.