2.4.8A/D Mode Control Register
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| Base+B : A/D Mode Control Register Format |
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Bit 7 | Bit 6 |
| Bit 5 | Bit 4 |
| Bit 3 |
| Bit 2 |
| Bit 1 | Bit 0 | ||||||||
X |
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| SI2 |
| SI1 | SI0 |
| X |
| D2 |
| D1 | D0 | ||||||
X=don‘t care |
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Mode Select |
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| Trigger Type |
| Transfer Type |
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D2 | D1 |
| D0 | Software Trig |
| Pacer Trig | Software | Interrupt |
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0 | 0 |
| 0 |
| Select |
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| X | Select |
| X |
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0 | 0 |
| 1 |
| Select |
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| X | Select |
| X |
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0 | 1 |
| 0 |
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| X |
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| X |
| X |
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1 | 1 |
| 0 |
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| X |
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| Select | Select |
| Select |
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X=disable |
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SI2 |
| SI1 |
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| SI0 |
| IRQ Level |
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| 0 |
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| 0 |
| 0 |
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| IRQ2 |
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| 0 |
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| 0 |
| 1 |
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| Not used |
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| 0 |
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| 1 |
| 0 |
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| IRQ2 |
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| 0 |
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| 1 |
| 1 |
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| IRQ3 |
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| 1 |
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| 0 |
| 0 |
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| IRQ4 |
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| 1 |
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| 0 |
| 1 |
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| IRQ5 |
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| 1 |
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| 1 |
| 0 |
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| IRQ6 |
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| 1 |
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| 1 |
| 1 |
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| IRQ7 |
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The A/D conversion operation can be divided into 2 stages, trigger stage and transfer stage. The trigger stage will generate a trigger signal to the A/D converter and the transfer stage will transfer the results to the CPU.
The trigger method may be an internal trigger or an external trigger. The internal trigger can be a software trigger or a pacer trigger. The software trigger is very simple but can not control the sampling rate very precisely. In software trigger mode, the program issues a software trigger command (sec. 2.4.9) any time needed. Then the program will poll the A/D status bit until the ready bit is 0 (sec. 2.4.2).
16 |