Omega Engineering IOP-241 user manual Port C Interrupt Description, External Interrupt Description

4.2Port C Interrupt Description

The eight Port C I/O channels (DATA23 - DATA16) may also be configured as interrupt sources. If any of these eight I/O channels are used to generate an interrupt, the I/O channel must be configured for input by latching the appropriate bit in the Data Port C Control Register to '1'. The interrupt must also be enabled by setting the appropriate bit in the Port C Interrupt Enable Register. Eight interrupt sources (INT7 - INT0) may be enabled in this manner; each of these interrupt sources corresponds to an I/O channel in Port C.

The mode of the port C interrupt sources may be configured in one of four possible manners: level sensitive active low interrupt, level sensitive active high interrupt, high-to-low transition edge sensitive interrupt and low-to-high transition edge sensitive interrupt. The lower nibble (4 bits) and upper nibble (4 bits) of the Port C interrupt sources may be configured separately. This will allow INT7 - INT4 to be configured for a different mode than INT3 - INT0. These modes are configured by writing the Interrupt Mode Control Register.

Whenever an interrupt is generated due to a Port C interrupt source, the corresponding bit of the Interrupt Status Register is set to reflect the cause of the interrupt. This provides a mechanism for determining the source of a detected interrupt. The Interrupt Status Register will be continually updated as additional interrupt generating conditions appear.

Writing a '1' to the appropriate bit of the Interrupt Acknowledge Register is the method by which interrupts should be acknowledged. After a write to the Interrupt Acknowledge Register, another interrupt will be generated if the Interrupt Status Register does not contain a value of 00h. Any bit in the Interrupt Status Register which has a value of '1' can be reset to a value of '0' if the following two conditions are met: first the corresponding bit in the Interrupt Acknowledge Register must be written with a '1' and second, the interrupt generating condition must no longer exist. For level sensitive interrupts, an interrupt will be immediately generated after the write of the Interrupt Acknowledge Register if the interrupt generating condition (active level on Port C interrupt source) remains.

4.3External Interrupt Description

In addition to the eight Port C interrupt sources, an additional external interrupt source is provided in the IOP-241. This external interrupt source is accessed through Pin 29 of the external connector. The external interrupt source permits the IOP-241 to be operated with 24-bit input/output and one separate interrupt source.

The Interrupt Mode Control Register provides a means of enabling/disabling this external interrupt, setting the external interrupt mode, reading the status of the external interrupt and acknowledging the external interrupt. The functionality of this external interrupt source is identical to that described for the Port C interrupt sources in the previous section.

IOP-241 Users Manual 24