Cypress CY7C1353G manual Features, Functional Description1, Logic Block Diagram

CY7C1353G

4-Mbit (256K x 18) Flow-through SRAM with NoBL™ Architecture

Features

•Supports up to 133-MHz bus operations with zero wait states

—Data is transferred on every clock

•Pin compatible and functionally equivalent to ZBT™ devices

•Internally self timed output buffer control to eliminate the need to use OE

•Registered inputs for flow-through operation

•Byte Write capability

•256K x 18 common IO architecture

•2.5V/3.3V IO power supply (VDDQ)

•Fast clock-to-output times

—6.5 ns (for 133-MHz device)

•Clock Enable (CEN) pin to suspend operation

•Synchronous self timed writes

•Asynchronous Output Enable

•Available in Pb-free 100-Pin TQFP package

•Burst Capability — linear or interleaved burst order

•Low standby power

Functional Description[1]

The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device).

Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.

Logic Block Diagram

A0, A1, A

ADDRESS

A1

A1'

REGISTER

D1

Q1

MODE

A0

D0

Q0

A0'

CE

ADV/LD

BURST

CLK

C

LOGIC

CEN

C

WRITE ADDRESS

REGISTER

O

U

T

S

D

P

A

U

ADV/LD

E

T

T

N

A

BWA

MEMORY

S

B

WRITE REGISTRY

WRITE

ARRAY

E

S

U

DQs

BWB

AND DATA COHERENCY

DRIVERS

A

T

F

DQPA

CONTROL LOGIC

E

F

DQPB

M

E

E

P

R

R

WE

S

I

S

E

N

G

INPUT

E

OE

REGISTER

READ LOGIC

CE1

CE2

CE3

ZZ

SLEEP

CONTROL

Note:

1.For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation	•	198 Champion Court • San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-05515 Rev. *E			Revised July 09, 2007

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