Cypress CY7B9910, CY7B9920 manual AC Timing Diagrams

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CY7B9910

CY7B9920

AC Timing Diagrams

Figure 1. AC Timing Diagrams

tREF

 

tRPWL

tRPWH

 

 

REF

 

 

tPD

tODCV

tODCV

 

 

 

FB

 

 

Q

 

 

tSKEW

 

tSKEW

OTHER Q

 

 

tJR

Figure 2. Zero Skew and Zero Delay Clock Driver

SYSTEM

 

 

 

 

FB

 

 

 

 

 

 

 

 

REF

 

 

 

CLOCK

 

 

 

FS

 

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

TEST

REF

Z0

Z0

Z0

Z0

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Document Number: 38-07135 Rev. *B

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Contents Features Block Diagram DescriptionLogic Block Diagram Functional DescriptionPin Configuration Test ModeSignal Name Description Pin DefinitionsAmbient Range Maximum RatingsOperating Range Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Switching CharacteristicsCapacitance Operating Clock FS = LOW 1 MHz Frequency in MHz FS = MID 1 FS = High 1, 2Zero Output Skew All Outputs 13 Output Rise Time 17Propagation Delay, REF Rise to FB Rise +0.7 Over the Operating Range11Device-to-Device Skew 8 Output Duty Cycle Variation +1.2AC Timing Diagrams AC Timing DiagramsOperational Mode Descriptions Board-to-Board Clock DistributionPackage Diagram Ordering InformationAccuracy Ordering Code Package Type Operating Range Pb-FreeIssue Date Orig. Description of Change Document History