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AC Switching Characteristics |
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SRAM Read Cycle |
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| Parameter | Description |
| 35 ns | Unit | |||
Cypress |
| Alt | Min |
| Max | |||
Parameter |
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tACE |
| tELQV | Chip Enable Access Time |
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| 35 | ns | |
tRC [5] |
| tAVAV, tELEH | Read Cycle Time | 35 |
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| ns | |
tAA [6] |
| tAVQV | Address Access Time |
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| 35 | ns | |
tDOE |
| tGLQV | Output Enable to Data Valid |
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| 15 | ns | |
tOHA [6] |
| tAXQX | Output Hold After Address Change | 5 |
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| ns | |
tLZCE [7] |
| tELQX | Chip Enable to Output Active | 5 |
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| ns | |
tHZCE [7] |
| tEHQZ | Chip Disable to Output Inactive |
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| 13 | ns | |
tLZOE [7] |
| tGLQX | Output Enable to Output Active | 0 |
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| ns | |
tHZOE [7] |
| tGHQZ | Output Disable to Output Inactive |
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| 13 | ns | |
tPU [4] |
| tELICCH | Chip Enable to Power Active | 0 |
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| ns | |
tPD [3, 4] |
| tEHICCL | Chip Disable to Power Standby |
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| 35 | ns |
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled [5, 6]
$''5(66
W5&
W$$
W2+$
'4'$7$287
'$7$9$/,'
Figure 6. SRAM Read Cycle 2: CE and OE Controlled [5]
$''5(66
&(
2(
'4'$7$287
,&&
W5&
W$&(
W/=&(
W'2(
W/=2(
W38 $&7,9(
67$1'%<
W3'
W+=&(
W+=2(
'$7$9$/,'
Notes
5.WE must be HIGH during SRAM Read Cycles.
6.I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
7.Measured ±200 mV from steady state output voltage.
Document Number: | Page 8 of 14 |
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