Cypress STK16C88-3 manual Write Cycle Time, Write Pulse Width, Chip Enable To End of Write

									STK16C88-3
Table 3. SRAM Write Cycle
	Parameter			Description				35 ns		Unit
Cypress		Alt					Min		Max
Parameter
tWC		tAVAV		Write Cycle Time			35			ns
tPWE		tWLWH, tWLEH		Write Pulse Width			25			ns
tSCE		tELWH, tELEH		Chip Enable To End of Write			25			ns
tSD		tDVWH, tDVEH		Data Setup to End of Write			12			ns
tHD		tWHDX, tEHDX		Data Hold After End of Write			0			ns
tAW		tAVWH, tAVEH		Address Setup to End of Write			25			ns
tSA		tAVWL, tAVEL		Address Setup to Start of Write			0			ns
tHA		tWHAX, tEHAX		Address Hold After End of Write			0			ns
tHZWE [7,8]		tWLQZ		Write Enable to Output Disable					13	ns
tLZWE [7]		tWHQX		Output Active After End of Write			5			ns
Switching Waveforms			Figure 7. SRAM Write Cycle 1:			Controlled [9]
					WE

	tWC
ADDRESS
	tSCE
CE
	tAW
	tSA
WE	tPWE
	tSD
DATA IN	DATA VALID
	tHZWE
	HIGH IMPEDANCE

DATA OUT PREVIOUS DATA

tHA

tHD

tLZWE

ADDRESS

CE

WE

DATA IN

Figure 8. SRAM Write Cycle 2: CE Controlled [9]

tWC

tSA tSCE tHA

tAW

tPWE

tSD tHD

DATA VALID

DATA OUT

Notes

HIGH IMPEDANCE

8.If WE is Low when CE goes Low, the outputs remain in the high impedance state.

9.CE or WE must be greater than VIH during address transitions.

Document Number: 001-50594 Rev. ** Page 9 of 14

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