Cypress STK16C88-3 Pin Configurations, Write Enable Input, Active LOW. When the chip is enabled

Page 2

STK16C88-3

Pin Configurations

Figure 1. Pin Diagram - 28-Pin PDIP

$

$

$ $ $ $ $

$ $ $ '4 '4 '4

966



 



 

 

9&&

 

 



 



 

 

 

 

 

 

 

 

 

 

:(

 

 



 



 

 

$ 

 

 

 

 



 



 

 

$ 

 

 

 

 

 

 

 

 

 

 

 



 



 

 

$ 

 

 

 

 

 

 

 

 

 



723



 

 

$

 

 

 

 





 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2(

 

 

 



 



 

 

$

 

 

 

 

 

 



 



 

 

 

 

 

 

 

 

 

 

 

 

 

&(

 

 

 



 



 

 

'4

 

 

 

 

 

 

 '4





 

 

 

'4

 

 





 

 

'4

 

 





 

 

'4

 

 

Table 1. Pin Definitions - 28-Pin PDIP

Pin Name

Alt

IO Type

Description

A0–A14

 

 

 

 

 

 

 

Input

Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.

DQ0-DQ7

 

 

 

 

 

 

 

Input or

Bidirectional Data IO lines. Used as input or output lines depending on operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Write Enable Input, Active LOW. When the chip is enabled and

 

is LOW, data on the

 

 

 

 

 

 

 

 

 

 

 

 

 

WE

 

WE

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IO pins is written to the specific address location.

 

 

 

 

 

 

 

 

 

 

 

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

 

 

CE

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

chip.

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Output Enable, Active LOW. The active LOW

 

input enables the data output buffers

 

 

 

 

 

 

 

 

 

 

 

OE

 

OE

 

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

VSS

 

 

 

 

 

 

 

Ground

Ground for the Device. The device is connected to ground of the system.

VCC

 

 

 

 

 

 

 

Power Supply

Power Supply Inputs to the Device.

Document Number: 001-50594 Rev. **

Page 2 of 14

[+] Feedback

Image 2
Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtOutput Enable, Active LOW. The active LOW Pin ConfigurationsWrite Enable Input, Active LOW. When the chip is enabled Power Supply Inputs to the DeviceSram Read Hardware Recall Power UpDevice Operation Sram WriteNoise Considerations Low Average Active PowerHardware Protect Best PracticesRead Sram Output Data 0x03E0 Software STORE/RECALL Mode Selection 13 a0x0E38 Read Sram Output Data Read Sram Output Data 0x303FOperating Range DC Electrical CharacteristicsMaximum Ratings Data Retention and EnduranceThermal Resistance CapacitanceAC Test Conditions Description Test Conditions Max UnitSram Read Cycle AC Switching CharacteristicsSwitching Waveforms Parameter Description 35 ns Unit Cypress Alt Min MaxAddress Setup to End of Write Chip Enable To End of WriteData Setup to End of Write Address Setup to Start of WriteLow Voltage Reset Level AutoStorePlus or Power Up RecallPower up Recall Duration Parameter Alt Description STK16C88-3 Unit Min MaxSoftware Controlled STORE/RECALL Cycle Parameter Alt Description 35 ns Unit MinPart Numbering Nomenclature STK16C88 3W F 35 Ordering InformationPackage Diagrams Pin 600 Mil PdipNew data sheet Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History