Control Logic Structures, SSCLK1a/b, S2 and S3

CY25566

SSCLK1a/b

SSCLK1a and SSCLK1b are spread spectrum clock outputs used for the purpose of reducing EMI in digital systems. SSCLK1a and SSCLK1b can be connected in several different ways to provide flexibility in application designs. Each clock can drive separate nets with a capacitative load up to 15 pF each or connected together to provide drive to a single net with a capacitative load as high as 33 pF. When both clocks are connected together, the CY25566 is capable of driving 3.3V CMOS-compatible clocks to frequencies as high as 200 MHz. If one clock output is not connected to a load, negligible EMI will be generated at the unused pin because there is no current being driven. The frequency and bandwidth of SSCLK1a and SSCLK1b is programmed by the logic states presented to S2 and S3. The frequency multiplication at SSCLK1a and SSCLK1b is either 1X or 2X, controlled by S2 and S3. The modulated output clock SSCLK1 is provided at pins 8 and 9 with each pin having separate but identical drivers. Refer to Figure 1 below.

Control Logic Structures

The CY25566 has six input control pins for programming VCO range, BW %, Mod ON/OFF and REFOUT ON/OFF. These programmable control pins are described below.

REFOFF

The output clock REFOUT can be enabled or disabled by controlling the state of REFOFF. When REFOFF is at a logic low(0) state, REFOUT is enabled and the reference clock frequency is present at pin 3. When REFOFF is at a logic high state (1), REFOUT is disabled and is set to a logic low state on pin 3. REFOFF has a 400-KW internal pull-up resistor to VDD.

S0 and S1 (Tri-level Inputs)

S0 and S1 are used to program the frequency range and bandwidth of the modulated output clocks SSCLK1a/b and SSCLK2. S0 and S1 of the CY25566 are designed to sense three different analog levels. With this tri-level structure, the CY25566 is able to detect 9 different logic states. Refer to

C Y 2 5 5 6 6

3 3 p f .

1 5 p f .

tables 5, 6 and 7 for the results of each of these 9 states. The level of each state is defined as follows:

Logic State “0” is a voltage that is between 0 and 0.15 × VDDV. Logic State “M” is a voltage between 0.4 × VDD and 0.6 × VDDV. Logic State “1” is a voltage between 0.85 × VDD and VDD.

Figure 2 illustrates how to program tri-level logic.

S2 and S3

S2 and S3 are used to program the CY25566 into different frequency ranges and multipliers. The CY25566 operates over a frequency range of 25 to 200 MHz and a 1X or 2X multipli- cation of the reference frequency. S2 and S3 are binary logic

Figure 1. SSCLK1a/b Driver Configurations

SSCLK2

inputs and each has a 400 K W pull-up resistor to VDD. See Table 1, Table 2, and Table 3 for programming details.

SCLK2 is a Spread Spectrum Clock with a frequency half that of the SSCLK1a clock frequency. When SSCLK1a is programmed to provide a 2.5% modulated clock at 1X times the reference clock, 40 MHz for example, the frequency of SSCLK2 will be 20 MHz with a BW of 2.5%. Note that by programming the frequency of SSCLK1a to 2X, the frequency of SSCLK2 will be 1X times the reference clock frequency.

SSCC

SSCC is an input control pin that enables or disables SSCG modulation of the output clock at SSCLK1a/b and SSCLK2. Disabling modulation is a method of comparing radiated EMI in a product with SSCG turned on or off.

The CY25566 can be used as a conventional low jitter multiple output clock when SSCC is set to low (0). SSCC has a 400-KW internal pull-up resistor. Logic high (1) = Modulation ON, logic low (0) = Modulation OFF. Default is modulation ON.

CY25566

S0 = "M" (N/C)
S0 = "M" (N/C)	13

S1 = "0" (GND)	12

SSCC = "1"	10

VDD

CY25566


S0 = "1"	13

S1 = "0" (GND)	12

SSCC = "1"	10

VDD

CY25566


S0 = "1"	13

S1 = "1"	12

SSCC = "1"	10

VDD

Figure 2.

Document #: 38-07429 Rev. *B

Page 3 of 9

[+] Feedback