Cypress STK14CA8 manual Features, Description, Logic Block Diagram

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STK14CA8

128Kx8 AutoStorenvSRAM

Features

25, 35, 45 ns Read Access and Read/Write Cycle Time

Unlimited Read/Write Endurance

Automatic Nonvolatile STORE on Power Loss

Nonvolatile STORE Under Hardware or Software Control

Automatic RECALL to SRAM on Power Up

Unlimited RECALL Cycles

200K STORE Cycles

20-Year Nonvolatile Data Retention

Single 3.0V + 20%, -10% Operation

Commercial and Industrial Temperatures

Small Footprint SOIC and SSOP Packages (RoHS Compliant)

Description

The Cypress STK14CA8 is a 1 Mb fast static RAM with a nonvol- atile QuantumTrap™ storage element included with each memory cell. This SRAM provides fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM.

Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.

The Cypress nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performing and most reliable nonvolatile memory available.

Logic Block Diagram

 

 

 

Quantum Trap

VCC

VCAP

 

 

 

 

 

 

 

 

 

A5

 

 

1024 X 1024

POWER

 

 

 

 

 

 

 

 

A6

DECODER

 

ARRAY

STORE

CONTROL

 

 

A12

 

RECALL

 

 

A7

 

 

 

 

 

 

 

A8

 

 

STATIC RAM

 

STORE/

 

 

A9

 

 

RECALL

 

 

 

 

 

 

 

 

 

A14

ROW

 

1024 X 1024

 

CONTROL

HSB

 

A13

 

 

 

 

 

 

 

 

A15

 

 

 

 

 

SOFTWARE

 

A16

 

 

 

 

 

A15 – A0

 

 

 

 

 

 

 

DETECT

 

DQ0

BUFFERS

 

COLUMN I/O

 

 

 

 

 

DQ1

 

 

 

 

 

 

DQ2

 

COLUMN DEC

 

 

 

 

 

DQ3

 

 

 

 

 

 

 

 

DQ4

INPUT

 

 

 

 

 

 

 

DQ5

A0

A1 A2 A3 A4 A10

A11

 

 

 

 

DQ6

 

 

 

 

 

 

 

 

DQ7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

W

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document Number: 001-51592 Rev. **

 

Revised March 04, 2009

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Contents Logic Block Diagram FeaturesDescription Cypress Semiconductor Corporation 198 Champion CourtPin Descriptions PinoutsPin Name Description Symbol Parameter Commercial Industrial Units Min DC CharacteristicsAbsolute Maximum Ratings AC Test Conditions Symbol Parameter Max Units ConditionsCapacitance Sram Read Cycles #1 and #2 Sram Write Cycles #1 and #2 Symbols Parameter AutoStore/POWER UP RecallUnits Standard Alternate Min Max Software Controlled STORE/RECALL Cycle Hardware Store Cycle Soft Sequence CommandsUnits Standard Alternate Min Units Standard Min Max16-A Mode Power Mode SelectionNvSRAM Operation Hardware Recall Power UpNvSRAM AutoStore OperationSoftware Recall Software StoreData Protection Noise ConsiderationsPreventing AutoStore Low Average Active PowerOrdering Codes Ordering InformationPin 300 mil Ssop Pin 300 mil SoicWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationNew data sheet Document History