Cypress STK14CA8 manual Pinouts, Pin Descriptions, Pin Name Description

Page 2

Pinouts

Figure 1. 48-Pin SSOP

STK14CA8

Figure 2. 32-Pin SOIC

VCAP 1

A16 2 A14 3

A12 4

A7 5

A6 6

A5 7

NC 8

A4 9

NC 10 NC 11 NC 12 VSS 13 NC 14 NC 15 DQ0 16

A3 17 A2 18 A1 19

A0 20 DQ1 21 DQ2 22 NC 23 NC 24

48 VCC

47 A15

46 HSB

45 W

44 A13

43 A8

42 A9

41 NC

40 A11

39 NC

38 NC

37 NC

36 VSS

35 NC

34 NC

33 DQ6

32 G

31 A10

30 E

29 DQ7

28 DQ5

27 DQ4

26 DQ3

25 VCC

VCAP

 

1

32

 

 

 

 

VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A16

 

2

31

 

 

 

 

A15

 

 

 

 

 

 

 

 

A14

 

3

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSB

 

 

 

 

 

A12

 

4

29

 

 

 

 

W

 

 

 

 

 

 

A7

 

5

28

 

 

 

 

A13

 

 

 

 

A6

 

6

27

 

 

 

 

A8

 

 

A5

 

7

26

 

 

 

 

A9

A4

 

8

25

 

 

 

 

A11

 

 

 

A3

 

9

24

 

 

 

 

 

G

 

A2

 

10

23

 

 

 

 

A10

A1

 

11

22

 

 

 

 

 

E

 

 

 

A0

 

12

21

 

 

 

DQ7

 

 

 

 

 

 

DQ0

 

13

20

 

 

 

DQ6

 

 

 

DQ1

 

14

19

 

 

 

DQ5

DQ2

 

15

18

 

 

 

DQ4

VSS

 

16

17

 

 

 

DQ3

Figure 3. Relative PCB Area Usage[1]

Pin Descriptions

Pin Name

I/O

 

 

 

 

 

 

 

 

Description

A16-A0

Input

Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.

DQ7-DQ0

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM.

 

 

 

 

 

 

 

 

Input

Chip Enable: The active low

 

 

input selects the device.

 

 

 

E

E

 

 

 

 

 

 

 

 

Input

 

Write Enable: The active low

 

 

 

allows to write the data on the DQ pins to the address location

 

 

W

W

 

 

 

 

 

 

 

 

 

 

latched by the falling edge of E.

 

 

 

 

 

 

 

Input

Output Enable: The active low

 

 

input enables the data output buffers during read cycles.

 

 

G

G

 

 

 

 

 

 

 

 

 

 

De-asserting G high causes the DQ pins to tri-state.

 

VCC

Power Supply

 

Power: 3.0V, +20%, -10%.

 

 

 

 

 

 

 

 

I/O

 

 

When low this output indicates a Store is in progress. When pulled low

 

HSB

Hardware Store Busy:

 

 

 

 

 

 

 

 

 

 

external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this

 

 

 

 

 

 

 

 

 

 

pin high if not connected. (Connection is optional).

VCAP

Power Supply

 

AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to

 

 

 

 

 

 

 

 

 

 

nonvolatile storage elements.

 

VSS

Power Supply

Ground.

 

NC

No Connect

Unlabeled pins have no internal connections.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

1. See Package Diagrams on page 15 for detailed package size specifications.

Document Number: 001-51592 Rev. **

Page 2 of 16

[+] Feedback

Image 2
Contents Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Name Description PinoutsPin Descriptions Absolute Maximum Ratings DC CharacteristicsSymbol Parameter Commercial Industrial Units Min Capacitance Symbol Parameter Max Units ConditionsAC Test Conditions Sram Read Cycles #1 and #2 Sram Write Cycles #1 and #2 Units Standard Alternate Min Max AutoStore/POWER UP RecallSymbols Parameter Software Controlled STORE/RECALL Cycle Units Standard Alternate Min Soft Sequence CommandsHardware Store Cycle Units Standard Min MaxMode Selection 16-A Mode PowerNvSRAM Hardware Recall Power UpNvSRAM Operation AutoStore OperationData Protection Software StoreSoftware Recall Noise ConsiderationsLow Average Active Power Preventing AutoStoreOrdering Information Ordering CodesPin 300 mil Soic Pin 300 mil SsopNew data sheet Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History