STK14CA8
SRAM WRITE Cycles #1 and #2
NO. |
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| Parameter | Units | |||||||
#1 |
| #2 | Alt. | Min | Max | Min | Max | Min | Max | |||
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12 | tAVAV |
| tAVAV | tWC | Write Cycle Time | 25 |
| 35 |
| 45 |
| ns |
13 | tWLWH |
| tWLEH | tWP | Write Pulse Width | 20 |
| 25 |
| 30 |
| ns |
14 | tELWH |
| tELEH | tCW | Chip Enable to End of Write | 20 |
| 25 |
| 30 |
| ns |
15 | tDVWH |
| tDVEH | tDW | Data Setup to End of Write | 10 |
| 12 |
| 15 |
| ns |
16 | tWHDX |
| tEHDX | tDH | Data Hold after End of Write | 0 |
| 0 |
| 0 |
| ns |
17 | tAVWH |
| tAVEH | tAW | Address Setup to End of Write | 20 |
| 25 |
| 30 |
| ns |
18 | tAVWL |
| tAVEL | tAS | Address Setup to Start of Write | 0 |
| 0 |
| 0 |
| ns |
19 | tWHAX |
| tEHAX | tWR | Address Hold after End of Write | 0 |
| 0 |
| 0 |
| ns |
20 | tWLQZ[5,7] |
| tWZ | Write Enable to Output Disable |
| 10 |
| 13 |
| 15 | ns | |
21 | tWHQX |
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| tOW | Output Active after End of Write | 3 |
| 3 |
| 3 |
| ns |
Figure 8. SRAM WRITE Cycle #1: W Controlled[7,8]
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ADDRESS |
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| 14 | 19 |
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| tWHAX | |
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| tELWH |
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E |
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| tAVWH |
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| tAVWL |
| 13 |
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W |
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| 15 | 16 |
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| tDVWH | tWHDX |
DATA IN |
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| tWLQZ | 21 |
DATA OUT |
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| HIGH IMPEDANCE | tWHQX |
| PREVIOUS DATA |
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ADDRESS |
E |
W |
DATA IN |
DATA OUT |
Figure 9. SRAM WRITE Cycle #2: E Controlled[7,8]
12
tAVAV
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18 |
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| 14 |
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| 19 |
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| tAVEL |
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| tELEH |
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| tWLEH |
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| tDVEH |
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| tEHDX |
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| DATA VALID |
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| HIGH IMPEDANCE |
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Notes
7.If W is low when E goes low, the outputs remain in the high impedance state.
8.E or W must be ≥ VIH during address transitions.
Document Number: | Page 6 of 16 |
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