AC Switching Characteristics
SRAM Read Cycle
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| Parameter | Description | 35 ns | 45 ns | 55 ns | Unit | ||||
| Cypress | Alt | Min | Max | Min | Max | Min | Max | |||||
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tACE |
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| tELQV | Chip Enable Access Time |
| 35 |
| 45 |
| 55 | ns | ||
t | RC | [4] |
| tAVAV, | Read Cycle Time | 35 |
| 45 |
| 55 |
| ns | |
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| tELEH |
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t | AA | [5] |
| tAVQV | Address Access Time |
| 35 |
| 45 |
| 55 | ns | |
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tDOE |
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| tGLQV | Output Enable to Data Valid |
| 15 |
| 20 |
| 35 | ns | ||
t | OHA | [5] | tAXQX | Output Hold After Address Change | 5 |
| 5 |
| 5 |
| ns | ||
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t | LZCE | [6] | tELQX | Chip Enable to Output Active | 5 |
| 5 |
| 5 |
| ns | ||
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t | HZCE | [6] | tEHQZ | Chip Disable to Output Inactive |
| 13 |
| 15 |
| 25 | ns | ||
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t | LZOE | [6] | tGLQX | Output Enable to Output Active | 0 |
| 0 |
| 0 |
| ns | ||
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t | HZOE | [6] | tGHQZ | Output Disable to Output Inactive |
| 13 |
| 15 |
| 25 | ns | ||
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t | PU | [3] |
| tELICCH | Chip Enable to Power Active | 0 |
| 0 |
| 0 |
| ns | |
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t | PD | [3] |
| tEHICCL | Chip Disable to Power Standby |
| 35 |
| 45 |
| 55 | ns | |
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Switching Waveforms
Figure 6. SRAM Read Cycle 1: Address Controlled [4, 5]
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W$$
W2+$
'4 '$7$287 
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Figure 7. SRAM Read Cycle 2: CE and OE Controlled [4]
$''5(66
&(
2(
'4 '$7$287
,&&
W5&
W$&(
W/=&(
W'2(
W/=2(
W38 
$&7,9(
67$1'%<
W3'
W+=&(
W+=2(
'$7$9$/,'
Notes
4.WE must be High during SRAM Read cycles.
5.I/O state assumes CE and OE < VIL and WE > VIH; device is continuously selected.
6.Measured ± 200 mV from steady state output voltage.
Document Number: | Page 7 of 15 |
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